We are using a C6726 on our custom board. When we are debugging are seeing a problem with seeming random register changes. For example when we step through an assignment that changes a variable that is place in an register (say A2) we see the value of another register (say A15) change at the same time. Turning off all optimization seems to fix the problem. What could be causing this?
The C6000 architecture can be difficult to follow if not familiar with it. The optimizer takes your code and packs it together as tightly as possible. This can cause confusing behavior as some instructions have inherent delay slots before execution finishes. For example, the LDW has 4 delay slots before execution completes; this means that the load will not complete until 4 CPU cycles after it is first invoked. This could explain why you see multiple registers changing when an instruction should change only one. Take a look at the C67xx DSP CPU and Instruction Set Reference Guide at section 3.4 and 3.10. Section 3.4 discusses delay slots and section 3.10 catalogs every instruction (including delay slots for that instruction).
-Tim
---------------------------------------------------------------------------------------------------------Please click the Verify Answer button on this post if it answers your question.---------------------------------------------------------------------------------------------------------
Tim,
Thanks for the reply. We may have found our problem. When we read a double out of SDRAM the value is corrupted. When looking at memory the lower 32 bits are correct but the upper 32 are duplicates of bits 15-8. We are investigating this.
Jim
This issue has been resolved. It was the same as the one posted by RAlwood (64-bit read issue on C6726 EMIF)
Thanks,