TI E2E Community
Digital Signal Processors (DSP)
C6000 Single Core DSP
C67x Single Core DSP Forum
Timer in DSK TMS320C6713
I am trying to create delay with timer. I have read in timer document that in 6713 processor timer run at (CPU clk/4), but I have confusions that it seems to me that it does not run (CPU clk/4), and also when I change DIV2 (peripheral clock) in PLL file delay also changes.
It is clear from the documentation that the timer runs at CPU/4. Why are you confused?
Do you have a way to confirm the CPU Clock speed to know that it is running at the speed you expect?
When you change DIV2, what other effects do you see, such as the CPU Clock changing? This should not happen, either.
Search for answers, Ask a question, click Verify when complete, Help others, Learn more.
Thanks for reply.
In TMS320C6713 timer run at SYSCLK/2.
SYSCLK2 rate must be half or less of SYSCLK1.
So if SYSCLK2 is half of SYSCLK1 then timer run at CPU/4 or SYSCLK/4.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.