I needed one of the above a few weeks ago and hunted these forums and the downloads and could never find one. It appears it is no longer part of the BSL.
I wrote one and am giving it to the community so no one else needs to reinvent the wheel. I didn't see an attachment mechanism so I pasted the code in place below. This blog editor mangled it pretty badly and I had to do manual patchup, so if it doesn't compile, it is likely 1-2 chars of typos.
TI, you can do better. As you can see, this isn't much code, but it does take TIME and TESTING to get a reliable package. This one is. I have been using it for several weeks and have turned cahce on/off/sizes and seen the measured code execution time effects.
TI, please consider including something like this in future BSL releases.
Thanks for considering it, Chris
Example usage:
CACHE_Init_L2 ( CACHE_L2MODE_DISABLED ) ; // I am using all of L2 for my fast arrays CACHE_Init_L1P ( CACHE_L1MODE_32KB ) ; CACHE_Init_L1D ( CACHE_L1MODE_32KB ) ;
evmc6748_cache.h: (I followed the naming convention so it even looks like it belongs in the BSL!)
#ifndef EVMC6748_CACHE_H
#define EVMC6748_CACHE_H
typedef enum {
CACHE_L2MODE_DISABLED= 0 ,
CACHE_L2MODE_32KB = 1 ,
CACHE_L2MODE_64KB = 2 ,
CACHE_L2MODE_128KB = 3 ,
CACHE_L2MODE_256KB = 4 , // this is the max available on the 6748 as of March 2012
CACHE_L2MODE_MAX = 7
} Cache_L2mode_t;
typedef enum {CACHE_L1MODE_DISABLED= 0 ,
CACHE_L1MODE_4KB = 1 ,
CACHE_L1MODE_8KB = 2 ,
CACHE_L1MODE_16KB = 3 ,
CACHE_L1MODE_32KB = 4 , // this is the max available on the 6748 as of March 2012
CACHE_L1MODE_MAX = 7
} Cache_L1mode_t;
#define CACHE_L2CFG ( (volatile uint32_t *) 0x01840000 )
#define CACHE_L1PCFG ( (volatile uint32_t *) 0x01840020 )
#define CACHE_L1DCFG ( (volatileuint32_t *) 0x01840040 )
voidCACHE_Init_L2 ( Cache_L2mode_tL2mode ) ;
extern voidCACHE_Init_L1P ( Cache_L1mode_tL1mode ) ;extern voidCACHE_Init_L1D ( Cache_L1mode_tL1mode ) ;
#endif
evmc6748_cache.h:
#include <evmc6748.h>
#include <evmc6748_cache.h>
extern voidCACHE_Init_L2 ( Cache_L2mode_tL2mode )
{
*CACHE_L2CFG = L2mode ;
}
extern voidCACHE_Init_L1P ( Cache_L1mode_t L1mode )
*CACHE_L1PCFG = L1mode ;
extern voidCACHE_Init_L1D ( Cache_L1mode_t L1mode )
*CACHE_L1DCFG = L1mode ;
<end of code and post>
And, this really should be able to work for almost any TI DSP, 2, 5, or 6. You just need to check the datasheet/Tech Ref for the reg values in hex to be changed and the enum choices available for that processor, but this code is a model that should work for all. At least I think...as Willy Wonka said, a little more testing is needed, Chris
Besides enabling the cache you must all set a memory attribute register (MAR) for external memory in order to allow it to be cached. APIs similar to what you've shown as well as APIs for the MAR bits are part of our DSP/BIOS RTOS, which I strongly suggest using as it is excellent. DSP/BIOS allows you to configure the cache either through a GUI or through run-time APIs. More details are available here:
http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache
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