What are the restrictions on Cache_wb() and Cache_inv() functions for address/byte count parameters?a. Should the address start on a cache line boundary? What happens when given address is not aligned with cache line boundary?b. Cache line size is 128 bytes for C6748. Is that correct?c. Should the byte count given be a multiple of cache line size? What happens when it is not?d. If is required that address needs to be aligned to a cache line boundary and size has to be a multiple of cache line size, is there some way to force the malloc()'ed buffers to align on a cache line boundary (other the round about way of allocating extra memory and aligning it at application level)
Documentation for those Cache APIs can be found here:
http://rtsc.eclipse.org/cdoc-tip/xdc/runtime/knl/Cache.html
The address you pass to the API, does not have to be cache line aligned, because the range of the addresses that the buffer covers is quantized to whole cache line. Similarly the byte count does not have to be multipe of cache line size. You are right, the C6748 cache line size is 128 bytes. It is a good practice to have the buffers aligned to cacheline boundary but is not a necessary condition.
However, the requirements of having buffers aligned to cache line boundary and having the the byte count as multiple of cache line size is more critical when if the application has GPP or the DSP using DMA to access shared buffers. This rule is part of the XDAIS standard and is very well documented in the wiki on Cache management given below:
http://processors.wiki.ti.com/index.php/Cache_Management#DMA-Related
To answer the last part of your question, to align any buffer to a given boundary the C6000 compiler supports the #pragma DATA_ALIGN() function. This function can be used to align buffers to the cacheline boundary without allocating extra memory.
Hope this answers all your questions.
Regards,
Rahul
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