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Digital Signal Processors (DSP)
C6000 Single Core DSP
C67x Single Core DSP Forum
Modification of PLL frequency on C6748
I use CCS5.1.0 and SYSBIOS 6.32 to develop an application on a C6748. I began developping on Logic PD evaluation board and now I use our specific board. But my board is equipped with a 13.1072MHz instead of 24MHz quartz mounted on evalutation board. I have modified the GEL file to a programming of PLL with a quartz of 13.1072MHz
device_PLL0(0,22,0,0,1,-1,-1); // Disablle SYSCLK for EMIFA and EMAC for quartz 13.1072 MHz : 13.1072*23=301.5MHz
instead of th efollowing programming for the evm board with a quartz of 24MHz
I have also modified the sysbios configuration file to set a CPU clock frequency of 301.5MHz.
But it does not work. It seems that the CPU works at 163.84MHz ... As if it takes into account tne basic programmming on evm board only : in fact 13.1072*25/2 = 163.84MHz.
Is it necessary to program PLL frequency somewhere else ?
I understand you're using 13.1072 MHz oscillator as a input clock.
More over you use POSTDIV=0 that means it defaults to 1.So,the CPU clock frequency could be 301.4656 MHz and also you can't move negative value to the POSDIV registers.
Please refer to the spruh79a.pdf Technical reference manual chapter 6 & 7 for the more detailed procedure to change the PLL Clock frequencies
This is made simpler using a PLL calculator spread sheet provided here: (Subtract 1 from the values configured while using it in the GEL files.)
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