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C6000 Single Core DSP
C67x Single Core DSP Forum
tms320c6745 bootloader bit error booting form nand
We have a board desing using a tms320c6745 dsp that boots from NAND flash.
We did a second bootloader that is written once in flash. We recently had some problems with a couple of boards that were used by clients for several months that stopped working. After investigation, it seems that 1 bit has corrupted over time in the flash. Some were stuck in our second bootloader waiting to get new code because the corrupted bit was in the main code and the others didn't even go into our boootloader because the bad bit was in this section. From what I understand form the bootloader datasheet, ecc detection is used but is some correction done??
Did any of you had similar issue with nand memory when one bit would change over time ?
What kind of NAND is used on the board? How many bit ECC does your NAND support? There is ECC based correction implemented in the boot loader and it supports upto 4 bit correction. Have you tried to run the debug GEL file to see if you can obtain any information from it:
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I am using micron MT29F2G08ABAEA 2gb flash. According to datasheet, it supports 4bit ECC.
I did not know such a gel file existed ! I ran it on a good board and on one that has the memory problem.
The description below the ROM Status is the interpretation of the Status code. ECC calculation is done in hardware by EMIF and the correction is setup by default in the bootloader. If you are seeing just one error on that NAND page then I would have assumed that it would be corrected by the bootloader. Another thing that you want to try is enabling the CRC while creating the AIS boot image to check for errors during loading of the code.
Another useful tip for you would be to follow the tip mentioned by Daniel on this post:
thanks Rahul, I will check that. I also downloaded the Ti's nand_writer that i will try to run in debug.
The thing I don't understand is that the device worked for several month and then stopped working. Also, crc would detect an error but would only try to reload it 3 times and stop so the device would still be in error.
So i programme my user bootloader using the nand writer program from Ti. I tried to simulate a bit error by doing the following.
The I read/backed-up all the sparebytes for ECC, modified one bit of the code and wrote it back in memory with the original sparebytes. I boot up and the device doesn't boot... Does that mean ecc correction does not work ? Is there something I can do so simulate a bit changing over time ?
I doubt whether the way you've simulated the ECC corruption is correct or not. But can you confirm the ECC algorithm used here? Is it 1-bit or 4-bit. And how many bits of corruption are you seeing per 512bytes of data? Also you might have to see whether the correction logic is enabled in your NAND driver.
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The corruption problem I have is during the TI boot loader part. If I understand correctly, there is supposed to be 4 bits ECC correction by default. Is there a way to enable/disable correction logic during the bootloader part ??? When I run the faulty board in debug mode and read the flash, there is one bit wrong on the whole block. I tought that maybe 5 bits are corrupted and only 4 are corrected but I don't know how I can validate/test this...
thanks for your support.
I have not worked on C6000 bootloaders. If you can share the code with me or point to the link where I can download the same version as yours I can check the support for ECC algorithm and correction logic implemented. If you can share the code please send it to email@example.com.
Pretty much all I used can be found here: http://processors.wiki.ti.com/index.php/Boot_Images_for_OMAP-L137
I used the flash utility to program my original flash in debug mode, and files are generated using AISgen. But there is no available source code for the TI bootloader.
I am not sure as to how the ECC algorithm is selected in case of AISGen. Can you please send the contents of a NAND page(2k + 64) along with the spare area bytes? From that we can figure out the algorithm used.
Also, have you explored the option of using UBL instead of AISGen? UBL source code is available. I'm not sure about AISGen source.
ECC bits generation on OMAPL138 is done in hardware by the EMIFA port. Basically the software (ROM boot loader) for correction logic follows the the NAND write cycle that is described on Page 733 of the C6745 Technical reference manual
I am not sure you can simulate the NAND bit error that occurs over time using software, because when you artificially create an error and write back , the EMIF hardware will calculate the ECC bits by default to align with the changed data.
Thanks both of you,
What I will do for know is I will write my sencondary bootloader using the nandwriter from TI to make sure ecc is used correctly at write. Other than that, I will have to wait and see if the problem is solve with that solution since it is pretty hard to reproduce.
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