This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[McASP] to detect BCLK clock error at I2S interface

Champs,

There are status registers of RSTAT and XSTAT at the McASP of C6000.

Before checking the register, is it possible to detect BCLK clock error at the I2S interface?

(Checking the clock status at lower hardware level.)

If it is not possible to detect clock level error, what is the right way to check the I2S communication error?

 

Thanks and regards,

Hayden

  • Hi Hayden,

    Thanks for your post.

    I don't think, there is a way to detect clock error at the i2S interface other than detecting CLKERR thru. XSTAT & RSTAT.

    One thing, you can do is to probe the CLK, FS & crresponding AXR[n] pins thru. an oscilloscope since I2S format is specifically designed to transfer a stereo channel (left and right) over a single data pin AXR[n]. Please refer section 23.1.5.1.2 in the c6748 TRM as below;

    http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

    Note: To transmit in I2S format, use MSB first, left aligned, and also select XDATDLY = 01,  RDATDLY = 01 ((1 bit delay) (refer Table 23-4 & Table 23-5 from the above TRM doc. )

    May be you can check this E2E post to validate McASP initialization with I2S format:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/283841.aspx

    Thanks & regards,

    Sivaraj K

    ---------------------------------------------------------------------------------
    Please click the
    Verify Answer button on this post if it answers your question.
    ---------------------------------------------------------------------------------