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C6748 : uPP receive problem

Hello,


I want to test the uPP on the DSP C6748. I wrote a little program that send a buffer of 100 bytes. The buffer is constituted of a counter that is counting from 0 to 99.

To receive the data, I configure the uPP in loopback mode.

When the interrupt EOW is activated, i 'm going to read the data and check them.

I put my test in a loop. Most of the time, the test is OK that is the received data are good (data are incremented from 0 to 99) but sometimes my test failed. In that case, I noticed that 8 bytes were always introduced in my data.

For example :"…… 37363534 3B3A3938 07060504 0B0A0908 3F3E3D3C 43424140 47464544 ……"  is received but  KO because of  the added "07060504 0B0A0908" sequence. The other data (before and after) are good.

I notice that the 8 bytes that are introduced are always the same "07060504 0B0A0908".

In my test I manage only 2 interrupts : timer interrupt (for my OS)  and  uPP interrupt.

I noticed  that if I disable  the timer interrupt , my test is always OK and never failed.

Thus finally I suppose that the interrupt interact with the functioning of the uPP but I don’t know How ?

I wanted to add that I tried to disable and enable global interrupt when I program read/write on uPP register (UPQD0/UPQD1/UPQD2, UPID0/UPQI1/UPQI2) but it didn’t change anything.

Any help would be appreciated, thank you very much in advance, Patrick

 

  • Hi,

    Have you configured the UPIER, UPIES,& UPISR registers to know interrupt status

    Are you getting any error cases?

    Have you configured the data formats properly?

    Refer the following TI wiki,

    http://processors.wiki.ti.com/index.php/Using_the_uPP_EVM_example_applications_from_the_BIOS_PSP

  • Firstly I would like to thank you for your answer.

    About your questions now :

    1 ) Yes I have configured the UPIER, UPIES and UPISR and I 'm getting any error when I fail in the problem.

    2 ) I have configured the data in 16 bits.

    See below how I have configured my different registers

    ####################"" begin start of code

        uppcr.field.FREE = 1; // Enable free run (ie emulation will not halt the peripheral)
        uppcr.field.SOFT = 0; // Soft stop disabled (ie emulation will not halt the peripheral)
        uppcr.field.RTEMU = 0; // Peripheral continues pending transaction while program is halted
        uppcr.field.EN = 0; // Peripheral disabled
        uppcr.field.SWRST = 0; // No reset

        upctl.field.MODE = UPP_ALL_DUPLEX1; //Channel A transmits and channel B receives
        upctl.field.CHN = UPP_DUAL_CHANNEL_MODE; // Dual channel mode
        upctl.field.SDRTXIL = 0; // Each channel has its own DMA
        upctl.field.DDRDEMUX = 0; // Each channel has its own DMA
        upctl.field.DRA = DUPP_CFG_DOUBLE_RATE; // Double data rate setting for A
        upctl.field.IWA = UPP_16BIT_WIDTH; // 16-bit interface for A
        upctl.field.DPWA = UPP_NO_PACK; // 16-bit interface for A
        upctl.field.DRB = DUPP_CFG_DOUBLE_RATE; // Double data rate setting for B
        upctl.field.IWB = UPP_16BIT_WIDTH; // 16-bit interface for B
        upctl.field.DPWB = UPP_NO_PACK; // 16-bit interface for B

        upicr.field.STARTPOLA = DUPP_CFG_START_POLARITY; // START polarity for A
        upicr.field.ENAPOLA = DUPP_CFG_EN_POLARITY; // EN polarity for A
        upicr.field.WAITPOLA = DUPP_CFG_WAIT_POLARITY; // WAIT polarity for A
        upicr.field.STARTA = DUPP_CFG_USE_WAIT_IN_RECV; // START used in RX mode for A
        upicr.field.CLKDIVA = DUPP_CFG_CLOCK_DIVISOR; // Clock divisor for A
        upicr.field.CLKINVA = DUPP_CFG_CLOCK_POLARITY; // Clock polarity for A
        upicr.field.TRISA = DUPP_CFG_HIGH_IMPED_STATE; // High-impedance state for A
        upicr.field.STARTPOLB = DUPP_CFG_START_POLARITY; // START polarity for B
        upicr.field.ENAPOLB = DUPP_CFG_EN_POLARITY; // EN polarity for B
        upicr.field.WAITPOLB = DUPP_CFG_WAIT_POLARITY; // WAIT polarity for B
        upicr.field.STARTB = DUPP_CFG_USE_WAIT_IN_RECV; // START used in RX mode for B
        upicr.field.CLKDIVB = DUPP_CFG_CLOCK_DIVISOR; // Clock divisor for B
        upicr.field.CLKINVB = DUPP_CFG_CLOCK_POLARITY; // Clock polarity for B
        upicr.field.TRISB = DUPP_CFG_HIGH_IMPED_STATE; // High-impedance state for B

        upivr.field.VALA = DUPP_CFG_IDLE_VALUE; // Idle value for A
        upivr.field.VALB = DUPP_CFG_IDLE_VALUE; // Idle value for B

        uptcr.field.RDSIZEI = DUPP_CFG_RX_THRESH; // RX thresh for I (A)
        uptcr.field.RDSIZEQ = DUPP_CFG_RX_THRESH; // RX thresh for Q (B)
        uptcr.field.TXSIZEA = DUPP_CFG_TX_THRESH; // TX thresh for A
        uptcr.field.TXSIZEB = DUPP_CFG_TX_THRESH; // TX thresh for B

    ################################ End start of code

    What it is very important to notice is that the problem occur only when the upp interrupt have to live with other interrupts (my timer interrupt for example) otherwise my test never fail.


    thank you for your analysis and next answer.

     

    Patrick.