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I cannot make timers work in 32-bit chainned mode in a TMS320C6748BZWT DSP

If I configure the timer in any other mode, it  works correctly but in 32-bit chained mode it doesn't count. I have set the Plus flag and I have tried all 4 timers too.

Are the timers of the TMS320C6748BZWT timer plus style timers? 

  • Hi,

    Thanks for your post.

    Please validate your 32-bit timer chained mode configuration procedure thru. section 29.2.1.4.2.1.1 & to enable the 32-bit timer chained mode, kindly check section 29.2.1.4.2.1.1 & section 29.2.1.4.2.1.2 for chained mode configuration procedure from the below c6748 TRM doc:

    http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

    Kindly check the above sections to ensure your configuration with dual 32-Bit Timers Chained Mode Example.

    Thanks & regards,
    Sivaraj K

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  • Hi Sivarja,

    This is the code I use (only the part refering to the timer  and it follows the spruh79a guidelines). Also, I've tried with all the fourtimers and I cannot see the TIM12 and TIM34 registers counting but in the rest o modes they do. The reload values are arbitrary to test the timers:

    #define TIMER_QN_BASE_ADDR (0x01C20000u)
    #define TMR_TGCR_PLUSEN (0x00000010u)
    #define TMR_TGCR_TIMMODE (0x0000000Cu)
    #define TMR_TGCR_TIM34RS (0x00000002u)
    #define TMR_TGCR_TIM12RS (0x00000001u)
    #define TMR_TCR_ENAMODE12 (0x000000C0u)
    #define TMR_TIM12 (0x10)
    #define TMR_TIM34 (0x14)
    #define TMR_PRD12 (0x18)
    #define TMR_PRD34 (0x1C)
    #define TMR_TGCR (0x24)
    #define TMR_REL12 (0x34)
    #define TMR_REL34 (0x38)


    // Select 32-bit chained mode (TIMMODE in TGCR).
    HWREG(TIMER_QN_BASE_ADDR + TMR_TGCR)=TMR_TGCR_PLUSEN | TMR_TGCR_TIMMODE;

    // Remove the timer from reset (TIM12RS and TIM34RS in TGCR).
    HWREG(TIMER_QN_BASE_ADDR + TMR_TGCR)=TMR_TGCR_PLUSEN | TMR_TGCR_TIMMODE | TMR_TGCR_TIM34RS | TMR_TGCR_TIM12RS;

    // Clear the timers.
    HWREG(TIMER_QN_BASE_ADDR + TMR_TIM12) = 0x0;
    HWREG(TIMER_QN_BASE_ADDR + TMR_TIM34) = 0x0;

    // Select the desired timer period (PRD12).
    HWREG(TIMER_QN_BASE_ADDR + TMR_PRD12) = 0x100;

    // Select the desired timer prescaler value (PRD34).
    HWREG(TIMER_QN_BASE_ADDR + TMR_PRD34) = 0x200;

    // Enable the timer (ENAMODE12 in TCR).
    HWREG(TIMER_QN_BASE_ADDR + TMR_TGCR)=TMR_TCR_ENAMODE12 | TMR_TGCR_PLUSEN | TMR_TGCR_TIMMODE | TMR_TGCR_TIM34RS |
    TMR_TGCR_TIM12RS;

    // If ENAMODE12 = 3h, write the desired timer period for the next timer cycle in the period reload.
    // This step can be done at any time before the current timer cycle ends.
    HWREG(TIMER_QN_BASE_ADDR + TMR_REL12) = 0x400;
    HWREG(TIMER_QN_BASE_ADDR + TMR_REL34) = 0x200;