Hello.
I have a question about Cache and L3 CBA RAM on C6747 DSP.
A document on C6747 says that L3 CBA RAM is non cacheable. The address of L3 CBA RAM is from 0x80000000 to 0x80020000.
But Memory Attribute Register 128 (MAR128) is set to 1 by default. I suppose that it means that Memory area from 0x80000000 to 0x8FFFFFFF will be cached by L1D and L2.
In this case, will the data in L3 be cached in L1D or L2?
I'm accessing L3 by CPU and DMA at the same time, and I'm having cache coherence problem.
Regards,
Shintaro