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EMIFA signal unusual on C6742

Other Parts Discussed in Thread: OMAPL138

Hi all,

I used OMAPL138EVM to develop C6742. 

The EMIFA_D5 and EMIFA_D6 pins had unusual signal when NAND flash did the R/W actions. Please refer the waveform that I got from EVM as follows.

May I ignore this problem or have the register to adjust this portion? Please give me some hints on this. 

Thanks in advance.

B.R.

OC

  • Hi,

    Are you getting any performance issues here due to this behavior ?

    Is the code that you are running own code or any TI provided ?

  • Hi Titus,

    Currently, I did not get the performance issues. I also used TI's code for this signal measuring. But I had some concerns that would be an unstable status when system loading was heavy.

    Did you have some workarounds to avoid this appearance or I can ignore it?

    Thanks a lot.

    B.R.

    OC 

  • Hello OC,

    Did you observe this waveforms in OMAPL138 EVM or C6742 custom board ?

    Did you check the waveform in other data pins ? 

    Regards,

    Senthil

  • OC,

    May I add some questions to Senthil's questions?

    Is the example trace captured during reads from the NAND Flash or writes to the NAND Flash?

    Other than the noise points that you are asking about, is the timing of the EMIF correct based on how you have programmed it?

    Regards,
    RandyP

  • Hi Senthil, Randy,

    Thanks a lot for your replies.

    The similar waveform can be seen at all data pins and is reading from NAND flash.

    And the waveform is measured from C6742 EVK.

    I want to clarify the waveform is normal on C6742 or not,

    If not, how to solve this phenomenon?

    Thanks in advance.

    B.R.

    OC

  • OC,

    This is not normal behavior for any processor-based board. You should look into trying another board, whether by borrowing or buying or replacing under warranty. Contact the board manufacturer or the distributor from whom you purchased the board. If you purchased the board from the TI eStore, there should be a return policy stated there with instructions.

    Regards,
    RandyP

  • Hi OC,

    Where did you probe these signals - at C6742 side or at NAND after the level translator?

    I think these slow ramp-ups (1) are due to tri-stated data line pulled high by the C6742's internal pull-up resistor during (hold+turnaround) period of read cycle. Rise rate depends on the pull-up resistor value (20...30 kOhm typical) and total capacitance of pins, connectors and traces (some tens of picofarads). Rise time is determined by the EMIFA timings: clock frequency and EMIFA_CEnCFG register value (R_HOLD and TA fields) for NAND. What are these values in your case?

    These short spikes at D6 (2) may be observed e.g. due to long ground wire of the scope probe at channel 2. 

    B.R.
      Denis