Hello,
I'm using uart1 interrupt to process continuous incoming data.
The setting is 115200 baud rate, FIFO mode(level 1), Tx interrupt disabled, Rx interrupt enabled.
I'm trying to send it 10 bytes packages continuously, but when I reduce the interval between packages to less than 4ms, the ISR only works fine for a while and will never be triggered again.
I deteced overrun error (OE bit = 1 in LSR ) when I stopped the CPU, but it get cleared later if I stop sending data to processor during these time.
I could no find any relation between the OE bit and interrupt so far.
Below is the register status viewed in CCS after the ISR never get triggered any more. I stoped in a random place in the program, but any place will see the same senarios.
By observation, the IPEND in IIR is always 0 (pending), and the data in RBR never change anymore.
Anybody met same problem or have any idea what might be the cause?
I'd love to provide more information if necessary.
Thanks!
=============================== UART Regs ==============================
UART1
RBR 0x000000A3 Receiver Buffer Register [Memory Mapped]
Reserved ************************ Reserved
DATA 0xA3 (Hex) Received data
THR 0x000000A3 Transmitter Holding Register [Memory Mapped]
Reserved ************************ Reserved
DATA ******** Data to transmit
IER 0x00000001 The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the CPU. [Memory Mapped]
Reserved **************************** Reserved
EDSSI 0 - DISABLE Enable Modem Status Interrupt
ELSI 0 - DISABLE Receiver line status interrupt enable.
ETBEI 0 - DISABLE Transmitter holding register empty interrupt enable.
ERBI 1 - ENABLE Receiver data available interrupt and character timeout indication interrupt enable.
IIR 0x000000C4 The interrupt identification register (IIR) is a read-only register at the same address as the FIFO control register (FCR), which is a write-only register. When an interrupt is generated and enabled in the interrupt enable register (IER), IIR indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. [Memory Mapped]
Reserved ************************ Reserved
FIFOEN 11 FIFOs Enabled Always 00b in Non-FIFO mode Set to 11b when bit 0 of the FCR register is set
Reserved ** Reserved
INTID 0x2 (Hex) - RDA Encodes the different types of interrupt
IPEND 0 - PEND Interrupt Pending This bit is used either in a hardwire prioritized (nirq) or polled interrupt system
FCR 0x000000C4 The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR), which is a read-only register. Use FCR to enable and clear the FIFOs and to select the receiver FIFO trigger level.The FIFOEN bit must be set to 1 before other FCR bits are written to or the FCR bits are not programmed. [Memory Mapped]
Reserved ************************ Reserved
RXFIFTL ** 0-3h Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared.
Reserved ** Reserved
DMAMODE1 * DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMOD1 = 1 is a requirement for proper communication between the UART and the EDMA controller.
TXCLR * Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit.
RXCLR * Receiver FIFO clear. Write a 1 to RXCLR to clear the bit.
FIFOEN * Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters.
LCR 0x00000003 The system programmer controls the format of the asynchronous data communication exchange by using LCR. In addition, the programmer can retrieve, inspect, and modify the content of LCR; this eliminates the need for separate storage of the line characteristics in system memory. [Memory Mapped]
Reserved ************************ Reserved
DLAB 0 - DISABLE Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If you use the dedicated addresses, you can keep DLAB = 0.
BC 0 - DISABLE Break control.
SP 0 - DISABLE Stick parity. The SP bit works in conjunction with the EPS and PEN bits.
EPS 0 - ODD Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits.
PEN 0 - DISABLE Parity Enable .The PEN bit works in conjunction with the SP and EPS bits.
STB 0 - 1BIT Number of Stop Bits Generated This bit specifies either one, one and a half, or two stop bits in each transmitted character. This bit is combined with the word length bits (LCR[1] and LCR[0]) determine the number of stop bits. The receiver clocks only the first stop bit regardless of the number of stop bits selected -------------------------------------------------------------------------------------------- Bit 2 Word Length Number of Stop Bits Generated -------------------------------------------------------------------------------------------- 0 Any word length 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2
WLS 11 Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits.
MCR 0x00000000 The modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes. [Memory Mapped]
Reserved ************************** Reserved
AFE 0 - DISABLE Autoflow control enable. Autoflow control allows the RTS and CTS signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. ---------------------------------------------------------------------- Bit 5 Bit 1 Autoflow Control Configuration ---------------------------------------------------------------------- 1 1 Auto-rts and auto-cts enabled 1 0 Auto-cts only enabled 0 X Auto-rts and auto-cts disabled
LOOP 0 - DISABLE Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature.
OUT2 0 - DISABLE
OUT1 0 - DISABLE
RTS 0 - HIGH RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved and should be cleared to 0. 0 RTS is disabled, CTS is only enabled. 1 RTS and CTS are enabled.
DTR 0 - DISABLE
LSR 0x00000061 LSR provides information to the CPU concerning the status of data transfers. LSR is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt. [Memory Mapped]
Reserved ************************ Reserved
RXFIFOE 0 - NOERROR Receiver FIFO error.
TEMT 1 - EMPTY Transmitter empty (TEMT) indicator.
THRE 1 - EMPTY Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated.
BI 0 - NOBREAK Break indicator. The BI bit is set whenever the receive data input (RX) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
FE 0 - NOERROR Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
PE 0 - NOERROR Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
OE 0 - NOERROR Overrun error (OE) indicator An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
DR 1 - READY Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated.
MSR 0x00000000 Modem Status Register [Memory Mapped]
Reserved ************************ Reserved
CD 0 - NOCD Complement of the Carrier Detect input When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)
RI 0 - NORI Complement of the Ring Indicator input When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)
DSR 0 - NODSR Complement of the Data Set Ready input When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)
CTS 0 - NOCTS Complement of the Clear To Send input When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)
DCD 0 - NODCD Change in DCD indicator bit DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated
TERI 0 - NOTERI Trailing edge of RI (TERI) indicator bit TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated
DDSR 0 - NODDSR Change in DSR indicator bit DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated
DCTS 0 - NODCTS Change in CTS indicator bit DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated
SCR 0x00000000 Scratch Pad Register [Memory Mapped]
Reserved ************************ Reserved
SCR 00000000 These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation.
DLL 0x00000051 DLL holds the least-significant bits of the divisor.This divisor latch must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. [Memory Mapped]
Reserved ************************ Reserved
DLL 01010001 The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator
DLH 0x00000000 DLH holds the most-significant bits of the divisor.This divisor latch must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. [Memory Mapped]
Reserved ************************ Reserved
DLH 00000000 The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator
PID1 0x44141102 The revision identification registers (REVD1) contain identification data for the peripheral. [Memory Mapped]
REV 01000100000101000001000100000010 Peripheral Identification Number
PID2 0x00000000 Revision ID Register 2 [Memory Mapped]
Reserved ************************ Reserved
TYP 00000000 Peripheral Identification Number
PWREMU_MGMT 0x00006003 Power Management and Emulation Register [Memory Mapped]
Reserved **************** Reserved
Reserved * Reserved. This bit must always be written with a 0.
UTRST 1 - ENABLE UART transmitter reset. Resets and enables the transmitter
URRST 1 - ENABLE UART receiver reset. Resets and enables the receiver
Reserved *********** Reserved
Reserved * This bit is always 1 . Writing this bit does not affect value
FREE 1 - RUN Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. In suspended mode, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events.
MDR 0x00000000 Mode Definition Register [Memory Mapped]
Reserved ******************************* Reserved
OSM_SEL 0 - 16xOVERSAMPLING Over-Sampling Select
