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EMIF addressing for async memory

tanisha bhatia
Prodigy 120 points

Hello,

I have to interface 512k X32 SRAM to C6727b using EMIF.

So, it needs 19 bit of address . how i have to exactly connect EMIF address and EM_BA pins? and do i need to use GPIO pins also for higher address?

Regards,

Tanisha

  • 0
    TI__Mastermind 43660 points

    Hello Tanisha,

    Have you selected the SDRAM part per your requirement ?

    Could you please share the SDRAM part number ?

    As you mentioned, you cannot assume directly the required number of address lines from 512K. The SDRAM addressing is completely different from NOR flash addressing.

    The SDRAM comprises row address, column address and bank address. The row address and column address are multiplexed under address lines. The required number of address lines must be available in SDRAM datasheet.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 120 points

    Hi Srinivasan,

    I am not using SDRAM but a SRAM at CS2 of asynchronous EMIF.

    The SRAM is 512K X32 bit. the functional block is as shown in image. Please suggest how to connect address bits of EMIF

    Regards,

    Tanisha

  • 0 in reply to tanisha bhatia
    TI__Mastermind 43660 points

    Hello Tanisha,

    The C6727B datasheet specifies (SPRS268E Figure 4.6)  that the additional address lines of NOR memory device can be configured using GPIOs.

    There is a note, Any GPIO-capable pins which can be pulled down at reset can be used to control A[18:14] for FLASH BOOTLOAD.

    I think the same can be implemented for SRAM interface too but not sure about the complexity involved in it.

    It seems one of the customer used GPIO bit banging to accomplish this requirement. Please refer below e2e thread for more details.

    https://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/int-c67x_single_core_dsps/f/433/p/58823/210428.aspx#210428

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 120 points

    Hi Senthil,

    I am Sorry but the link you sent is not opening, it says group not found.

    I have read about GPIO pins being used as higher address pins  but if you can provide some help how to connect it to internal address being generated when i call base address +offset from EMIF, it will be really useful.

    I have to connect two external devices SRAM 512k X 32(19 address lines) and EEPROM 128K X 8(17 address lines) on same emif CS2, is it possible and if so both will get CS from EMIF CS or i should use some other pin as i have to distinguish between both when i access it using EMIF?

    EEPROM will be used at boot time only, code will be read drom EEPROM and written to SRAm. Later only SRAM will be used for data writing and reading purpose.

    Regards,

    Tanisha

  • 0 in reply to tanisha bhatia
    TI__Mastermind 43660 points

    Hello Tanisha,

    The important statement in the given e2e link is below.

    Ref: Internal E2E Thread

    I believe that your max async memory space is limited by the number of bit-bang GPIO pins that you want to support.  Typically, you would create a software layer for memory fetches that will decode the memory address into GPIO bit-bang configurations on the higher address lines and let EMIF handle the lower address lines.

    I do not know how to access the internal memory addresses using GPIO and i hope we do not have any example too.

    You may search in the internet to get more details about this.

    Tanisha Says said:

    I have to connect two external devices SRAM 512k X 32(19 address lines) and EEPROM 128K X 8(17 address lines) on same emif CS2, is it possible and if so both will get CS from EMIF CS or i should use some other pin as i have to distinguish between both when i access it using EMIF?

    In my opinion, you cannot connect two devices on same EMIF CS2.

    Regards,

    Senthil