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Connecting McBSP to SAR ADC

Mohsen Jamalabdollahi
Prodigy 80 points

Hello,

How can we prog the CLKRx of McBSP in C6713 to stay low for a while (change from clocking to low by FSRx) and start to clocking by changing the value of DRx until the next FSR?  In other word, I need the McBSP's output CLK stays low at SAR conversation phase and start clocking at data conversation phase between two consecutive FSX.

  • 0
    TI__Guru* 84110 points

    Mohsen,

    All of the available programmable modes of the C6713 McBSP are described in the McBSP Reference Guide. Please review that document to see if there are any modes that would work for you.

    You may want to search for things like "stopping clocks". That section might be similar to what you want to do, but you will have to consider it against what your requirements actually are. Or it may be that other modes would be better, if there is one that would work for you.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 80 points

    Dear RandyP,

    Here I attached my McBSP config. I am trying to use CLKST setting on  but no way to stop it. I have study the McBSP manual as much as I could but found nothing that help me on that.  All other parts of McBSP work perfectly but this is the first issue that I had and never solved. The CLK just doesn't stop after receiving the sample.

    config.spcr = (Uint32)
    ((MCBSP_SPCR_FRST_0 << _MCBSP_SPCR_FRST_SHIFT)
    | (MCBSP_SPCR_GRST_1 << _MCBSP_SPCR_GRST_SHIFT)
    | (MCBSP_SPCR_XINTM_XRDY << _MCBSP_SPCR_XINTM_SHIFT)
    | (MCBSP_SPCR_XSYNCERR_NO << _MCBSP_SPCR_XSYNCERR_SHIFT)
    | (MCBSP_SPCR_XEMPTY_1 << _MCBSP_SPCR_XEMPTY_SHIFT)
    | (MCBSP_SPCR_XRDY_NO << _MCBSP_SPCR_XRDY_SHIFT)
    | (MCBSP_SPCR_XRST_0 << _MCBSP_SPCR_XRST_SHIFT)
    | (MCBSP_SPCR_DLB_OFF << _MCBSP_SPCR_DLB_SHIFT) 
    | (MCBSP_SPCR_CLKSTP_NODELAY << _MCBSP_SPCR_CLKSTP_SHIFT)
    | (MCBSP_SPCR_RINTM_RRDY << _MCBSP_SPCR_RINTM_SHIFT)
    | (MCBSP_SPCR_RFULL_NO << _MCBSP_SPCR_RFULL_SHIFT)
    | (MCBSP_SPCR_RRDY_YES << _MCBSP_SPCR_RRDY_SHIFT )
    | (MCBSP_SPCR_RRST_1 << _MCBSP_SPCR_RRST_SHIFT));

    config.rcr = (Uint32)
    ((MCBSP_RCR_RPHASE_SINGLE << _MCBSP_RCR_RPHASE_SHIFT )
    | (MCBSP_RCR_RCOMPAND_MSB << _MCBSP_RCR_RCOMPAND_SHIFT)
    | (MCBSP_RCR_RFIG_NO << _MCBSP_RCR_RFIG_SHIFT ) 
    | (MCBSP_RCR_RDATDLY_1BIT << _MCBSP_RCR_RDATDLY_SHIFT ) 
    | (MCBSP_RCR_RFRLEN1_OF(0) << _MCBSP_RCR_RFRLEN1_SHIFT ) 
    | (MCBSP_RCR_RWDLEN1_16BIT << _MCBSP_RCR_RWDLEN1_SHIFT ));

    config.srgr = (Uint32)
    ((MCBSP_SRGR_CLKSM_INTERNAL << _MCBSP_SRGR_CLKSM_SHIFT )
    | (MCBSP_SRGR_FSGM_FSG << _MCBSP_SRGR_FSGM_SHIFT )
    | (MCBSP_SRGR_FPER_OF(40-1) << _MCBSP_SRGR_FPER_SHIFT)
    | (MCBSP_SRGR_FWID_OF(0) << _MCBSP_SRGR_FWID_SHIFT)
    | (MCBSP_SRGR_CLKGDV_OF(8-1) << _MCBSP_SRGR_CLKGDV_SHIFT));

    config.pcr = (Uint32)
    ( (MCBSP_PCR_FSXM_EXTERNAL << _MCBSP_PCR_FSXM_SHIFT)
    | (MCBSP_PCR_FSRM_EXTERNAL << _MCBSP_PCR_FSRM_SHIFT)
    | (MCBSP_PCR_CLKXM_OUTPUT << _MCBSP_PCR_CLKXM_SHIFT)
    | (MCBSP_PCR_CLKRM_OUTPUT << _MCBSP_PCR_CLKRM_SHIFT)
    | (MCBSP_PCR_FSXP_ACTIVEHIGH << _MCBSP_PCR_FSXP_SHIFT)
    | (MCBSP_PCR_FSRP_ACTIVEHIGH << _MCBSP_PCR_FSRP_SHIFT)
    | (MCBSP_PCR_CLKXP_RISING << _MCBSP_PCR_CLKXP_SHIFT)
    | (MCBSP_PCR_CLKRP_RISING << _MCBSP_PCR_CLKRP_SHIFT));

    As you see the FPER has been set for 40clks while the input sample is 16bits which must be trasfered after 16clks. I need the clk to be stopped after 16 clks where sample reception is accomplished by McBSP and stays low or high till the next FSR but it never stops generation clk.

    Thank you so much in advance,

    Mohsen