C6746 - Winbond DDR2 interfacing issues

Hi Bogdon,

I have tried the below code on C6748LCDK board and I'm able to read and write on DDR memory.

Please try the below code and update the results.

volatile unsigned int *data1 = (volatile unsigned int *)0xC0000000;


void main (void)
{

	int i;

	for (i=0;i<20;i++)
		data1[i] = 0;

	*data1++ = 0x4;

	*data1++ = 0x8;

	*data1++ = 0xBC;

	*data1++ = 0xF2;

	*data1++ = 0x5;

	*data1++ = 0x12;

	*data1++ = 0xFE;

	*data1++ = 0x2A;

	while(1){

	   }
}

Have you modified the SDRAM timing registers as per your DDR2 data sheet ?

http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

Hi Titus,

I will take a look over the DDR datasheet and try to use the excel file to compute the regs. I'll get back to you tomorrow with the progress. Thank you.

Regards,

Hello again, 

So, I have been struggling with the DDR for the last couple of days.

The first issue, the one regarding the appearance of '1' within the DDR values was fixed. It turned out it was a hardware issue.

The problem with the data being overwritten however, I could not fix. I modified the SDTIMR1 & 2 as per your instructions and I took into consideration the note from the C6746 technical manual (page 307), advising me to "relax" the timing values in order to compensate for the signal delays introduced by the board layout. Still, the problem persisted.

I made another simple program that modifies multiple consecutive DDR addresses at the same time. The program is:

for (i=0;i<20;i++)

data1[i] = 0x0000;

for (i=0; i<4; i++){

                data1[0] = i;

                data1[1] = i+1;

                data1[2] = i+2;

                data1[3] = i+3;

                data1[4] = i+4;

                data1[5] = i+5;

                data1[6] = i+6;

                data1[7] = i+7;

                data1[8] = i+8;

                data1[9] = i+9;

                data1[10] = i+10;

                data1[11] = i+11;

                data1[12] = i+12;

                data1[13] = i+13;

                data1[14] = i+14;

                data1[15] = i+15;

                data1[16] = i+16;

                data1[17] = i+17;

                data1[18] = i+18;

                asm(" nop");

}

The results at each “i” are presented in the table below. The bold font was used for the values that change along with the increment of i.

There seems to be a pattern in the values (at least for the first 4 memory addresses) but I cannot tell what can be the cause of such behavior.

Could it be a software issue (PAGESIZE, IBANK fields not having correct values – even though I double checked everything), memory incompatibility or a hardware issue (parasitic capacitances, line impedances etc.)?

Regards,

Hi Bogdon,

Is there any update on DDR issue ?

Where your code reside to run ?

internal RAM ?

Could you please try to run your any sample program on DDR by modifying the linker command file ?

Try the below code on your DDR and update the behavior.

volatile unsigned int *data1 = (volatile unsigned int *)0xC0000000;
void main (void)
{
    int i;
    for (i=0;i<20;i++)
        data1[i] = 0;
    *data1++ = 0x4;
    *data1++ = 0x8;
    *data1++ = 0xBC;
    *data1++ = 0xF2;
    *data1++ = 0x5;
    *data1++ = 0x12;
    *data1++ = 0xFE;
    *data1++ = 0x2A;
    while(1){
       }
}

Also try to run the program on CCS and let me update the results.

5315.ddr_test_out.txt

Note:

Rename ddr_test_out.txt to ddr_test.out

hi Titus,

It's Bogdan btw :)

I have tested the code you sent several times but the same problem arises. My code runs in the internal RAM for now. I only wanted the data section to be sent to the external RAM.

I didn't quite understand what you meant by:

"Also try to run the program on CCS and let me update the results.

5315.ddr_test_out.txt

Note:

Rename ddr_test_out.txt to ddr_test.out"

Do you want me to load the ddr_test.out file on my target configuration and run it? If that is so, I have already tried it (from: Run->Debug Configurations; I select my project's platform and the .out you have sent me with the modifications you mentioned; I load the program and click debug). The following error appears:

'C674X_0: GEL: Encountered a problem loading file: C:\Projects\_CCS\First3\Debug\ddr_test.out Could not determine target type of file'

But, again, I must stress that the issue lies in the way the data is put into the DDR (the addressing). By analyzing the data being sent to the DDR in the Memory Browser, I can see that the values that are stored in the DDR are correct. The placement, however is wrong...

Regards,  

You are absolutely right regarding the size! I searched the winbond datasheet again and I also found that the page length is expressed in bits (512 bits), while the page size in the C6746 Technical Reference Manual (page 293) is expressed in words.. Is this a compatibility issue or is it the same thing expressed in different ways (since the number of column address bits seem to match)? 

Anyway, I have changed the DDR mem length in the .gel and .cmd as per your instructions, but no improvement.. 

I think I will change the RAM to something closer to the one you use on the evaluation board.

Thanks for the great support!

Hi Bogdan,

Have you tried anytime to load any DSP program (all sections) on DDR2 by changing the linker command file ?

Update me if you are running into any issues when you load app on DDR2.

C6746.cmd:

SECTIONS                                      

{                                             

    .text          >  DDR2

    .stack         >  DDR2

    .bss           >  DDR2

    .cio           >  DDR2

    .const         >  DDR2

    .data          >  DDR2

    .switch        >  DDR2

    .sysmem        >  DDR2                   

    .far           >  DDR2

    .args          >  DDR2

    .ppinfo        >  DDR2

    .ppdata        >  DDR2

 

    /* COFF sections */

    .pinit         >  DDR2

    .cinit         >  DDR2

 

    /* EABI sections */

    .binit         >  DDR2

    .init_array    >  DDR2

    .neardata      >  DDR2

    .fardata       >  DDR2

    .rodata        >  DDR2

    .c6xabi.exidx  >  DDR2

    .c6xabi.extab  >  DDR2

}

 

Is this a compatibility issue or is it the same thing expressed in different ways (since the number of column address bits seem to match)?

This is not a problem, some people would mention in bits instead of using bytes.

Yes, the following error pops:

C674X_0: Output: Target Connected.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Cleared.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Setup Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PSC Enable Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PLL0 init done for Core 400Mhz, DDR Clock 100Mhz
C674X_0: Output: DDR initialization is in progress....
C674X_0: Output: PLL1 init done for DDR:100MHz
C674X_0: Output: VTP Ready
C674X_0: Output: Using DDR2 settings
C674X_0: Output: DDR init for 100 MHz is done
C674X_0: Output: ---------------------------------------------
C674X_0: File Loader: Data verification failed at address 0xC0004000 Please verify target memory and memory map.
C674X_0: GEL: File: C:\Projects\_CCS\First3\Debug\First3.out: a data verification error occurred, file load failed.