McAsp IT based echo APP

Hi Louis,

At what frequency are you running the C6748 LCDK board ?

EDMA is the faster one.

How did you say and confirm that you have delay between i/p and o/p ?

Hi Titus S,
Thanks for your prompt reply.

@ 300 MHz but we might need the 450MHz mode... Yes, the delay is acceptable in the audio world but not in the instrumentation. It almost inverts the 100Hz sine I connected to LINE1 input, so the phase *** is around 180°.

We need to process every samples and output the (A+B)/2 on the LINE2 port. This drives a vibrating system on resonant frequency so the delay must be some nanosecs on 100-1000Hz range.

In 2003 I implemented it with Silicon Labs 8-bit, 25MHz MCU. Now we need a newer version + new functions and DSP. Unfortunately the DMA can’t play in this team.

Best regards,
Louis

Hi,
Thanks for the reply.

Yes, I already knew that sample. I already downloaded and installed it and I realized that it won’t run on LCDK dev. kit: I have to modify the initialization (macro def) part of the demo APP in order to run on my LCDK dev. kit. And this porting between platforms was the reason why I asked the community. Maybe somebody already did it and I need not reinvent the wheel.

90% of the EVM sample is low level HW initialization of the chips (even parts written in assembly). Do you really think that I can do this porting with all of my 10 days practice with this processor? Wow, many thanks for the trust! So I have to go through almost every line of the EVM demo app code and translate the magical macro commands from EVM platform to LCDK platform. Give me a year and I can do that. It is simpler if I buy an EVM dev. kit and throw out the LCDK dev. kit.

By the way, low level HW initializing: Does TI have a graphical peripheral configurator wizard APP for C6748 CPU? I am talking about a graphical windows APP in which you can select say the McAsp port (or any subsystem timer, EDMA, UART, USB…), and the APP shows all the properties of the selected device, the current settings, and your choices enable/disable things. When you finished then it generates the necessary initialization code. This works just fine for many of processors I used. TI should have such an APP also… I just could not find it…
Thanks,
Louis

Hi,

Thanks for your update.

I don't think, TI has such graphical window APP which you are talking about in your post, but any way thanks for your recommendation to TI. Instead, you have all packed inside the TI proprietary CCS development *** debugging tool, in which you could explore all features like watch window, memory view, register view to describe the status of each selected device/peripheral and System analyzer/UIA tool comes as part of CCS to debug with graphical display window to show the properties of each selected device and its configuration etc.

We generally use oscilloscope to probe the signal and tap the data at appropriate test points on the H/W board to evaluate & analyze the clocks/ framesync. data signals. etc

Thanks & regards,

Sivaraj K

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Hi Sivaraj,
No configurator APP? That’s bad news. But I love the graph functions, very smart!!!

Anyway I managed to get McAsp interrupts. I spent 18 hours with comparing and try to understand what the LCDK and what the EVM demo initializes. Finally I got data from the CODEC via McAsp. I could plot the received data on a graph and it shows the input sine. The problem is that I have 100 Hz input sine, which means 10 ms period time. I found two successive positive peak codes on the graph. The first was sample 102 the next at sample 402. This means 300 samples per one period sine wave. Nice. Now the set sampling frequency is 48kHz. The 300 samples (1 period) takes 300 * (1/48000) = 6.25 ms. Instead of 10 ms. The 6.25 ms means 160 Hz??? What is wrong?

The other question is: When the McAsp RX data ready interrupt happens what the McASPRxBufRead() function does read? It is a 16-bit integer (right my world length is 16-bit) padded with another 16 zeros. What I read is a sample of the sine but on which channel of the CODEC? Or the first (and odd) number of interrupts returns the left channel data while the next interrupt the right channel data? Or what.

Writing back the received data when the TX data ready interrupt happens does not work. I mean the TX data ready IT happens, and I write back what I read in the last RX data ready IT but there is no output signal in the LINE1 outputs. There are scope probes on the LINE1 IN L/R pin and on the LINE1 OUT L/R pins. The input is okay but the output is always 0.

Can you help?
Many thanks for your help.
Louis

PS: Can you tell me which document (manual) and where contains the RESOLUTION and the voltage reference value of the ADC and DAC? The SLAS663B is not that document. Try to find 24-bit(s), 24 bit, voltage reference, band gap. I suppose it has 24-bit resolution and 2.5V reference voltage. Is this true?

Hi Mike,

Thanks for the info and your help. Interesting.

The interrupt based APP works on the LCDK. With limitations:

• The CODEC uses capacitive coupling (100nF) on the inputs.
• The capacitance difference between channels causes 18-60 usec phase shift (if you drive the LINE1L and LINE1R from the same signal).
• The codec can not work from ground symmetrical inputs.
• The differential inputs (LINExL- and LINExR-) are not connected to any pin of the LCDK.

The next step is to build an extension card with an external ADC which:

1. Resolution (24-bit) and voltage reference (+2.5V) are specified in the user’s manual
2. Can measure ground symmetrical input signals
3. Starts the left and right channel ADC at the same time
4. The converted left and right channel data can be read at the same time via SPI bus. (TI Codec returns the left channel data first, then the right channel data in two successive frames. I just can hope the left and right channel results belong to the same sample...)

This ADC exists. Not a cheap one. Not TI product. Does anybody know a CODEC which the above 4 properties?

Thanks guys for your help!
Best regards,
Louis

Hi,
Thanks for the samples (Sivaraj) and for the notice (Mike). I will give a try.
Best regards,
Louis

Sivara

This example is ridiculously complex. It is also entangled with DSP/BIOS, which I do not want to use. It would take me weeks to pick out the appropriate code, which I do not have time to do.

Why don't you do this for us?

Hi Mike

This thread has got a bit confusing with what Louis is originally requesting vs what you are asking for with reference to older threads :). 

Can you clarify what you are looking for us to help with? I think you are asking us to have an updated Starterware example (non OS) , with EDMA, working on LCDK, that does not have some of the issues that you highlighted. Please confirm. 

You are absolutely right that c6748/OMAPL138 remains a compelling/good part with float/fixed capabilities, right mix of power/performance/cost and good set of diverse peripherals even though it is almost 7 yrs old :). 

The challenge we have is that Starterware for OMAPL138 is now available "as-is" and there are no updates planned.

Some of this captured in the wiki here

http://processors.wiki.ti.com/index.php/OMAPL138_SW_%26_HW_Comparison#FAQ

which we encourage new OMAPL138/C6748 developers to look at ,on why McSDK, why LCDK etc. Yes there maybe start up issues starting with a new bundle and more so if the intent was to look for a starterware like or quickstartrcsl like code-base, but for full production suite, McSDK is the way to go. 

Although, right now there are no plans to upgrade/update Starterware for this family, but perhaps over coming months we can try to address just the McASP+EDMA starterware example and push it on a stand alone wiki.

So it would be great if you could regurgitate what you are looking for in this or preferably a separate thread.

I have highlighted this thread to our product marketing team and will keep an eye for any additional feedback you might have. 

Regards

Mukul 

Hi Mukul,

When we originally purchased the LCDK kit (CCS6 and the emulator) then we thought using the McAsp audio sample with the TI CODEC on board would work for us for a phase measurement demo application. But, the McAsp audio sample app collects 2000 bytes from McAsp port using EDMA and stores the samples using ping-pong buffers. The McAsp is set to 32-bit mode so the 2000 bytes means 62 samples. The time is necessary to collect the samples is 62 /48000 (@48kHz sampling) ~ 1.3ms. Therefore the samples will be sent out using the DAC of Codec 1.3 ms later than they have been collected. This is acceptable for an audio APP but not for a measurement tool.

When I realized this I moved to the interrupt driven approach. This has 1/Fs (22usec) delay only which is still acceptable. When the read IT happens we calculate the (left + right) / 2 and write it immediately back to the DAC. After this we store the input samples into an array and run FFT using the CPU’s DSP chip to determine the phase difference, magnitude, frequency, etc…

HW problems: Unfortunately the CODEC uses capacitive coupling for the input channels which is the largest enemy of phase measurement. The CODEC’s differential inputs are not connected to any pins of the LCDK but the diff. inputs also need capacitive coupling. Finally the codec can not process ground symmetrical signals. Useless for us. This is why we need an extension card with right ADC converter on it. I plan to use the SPI1 signals to control the external ADC because I found in the Camera flat ribbon cable connector. It has CS lines, so I do hope it will work.

Is this clear or I misunderstood something?

Many thanks for your help.
Louis

PS.: The C6748 is seven years old? Can you suggest a similar CPU+DSP which is newer or replacement of the C6748 chip. I should not base a brand new product on a 7 years old processor.

Mukul,

Thank you for the input. I have restated my request here:

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/376334.aspx

Hi Louis

Thanks for taking the time out to spell out your requirements. I do see how the current set of examples and our eval board might not be a good fit for you and there maybe a need for delta hardware and software on your side to make this work. 
Unfortunately I do not have any good suggestions, to provide any immediate respite or shorten your dev effort, but please feel free to post follow up questions on c6748 aspects , that become a road block as you progress.

PS.: The C6748 is seven years old? Can you suggest a similar CPU+DSP which is newer or replacement of the C6748 chip. I should not base a brand new product on a 7 years old processor.

Sorry perhaps misspoke a bit , as I am counting internal development years. The device was announced in ~2009 time frame, if I recall correctly and is still being used for new designs. There are ofcourse newer devices available and whether or not it will work for you , will depend on your performance, cost, power and integration requirements. This is likely still a very good choice if you are looking for a lower cost, low power float/fix DSP. It has a wide appeal across several end applications. 

Hi Mukul
Ok, thanks for the answers.

Our IT based APP is better and better, it works nice but the null phase difference (when you connect the same signal to both inputs) is frequency dependent. It is 16.5usec @ 100Hz, 17.2usec @110Hz and almost 20usec @200Hz. This is because of the capacitive signal coupling on the inputs of the CODEC ADC in the LCDK kit.

But – of course - I have a couple of stupid questions.

1. Can you tell me the reference voltage and resolution (24-bit?) of the CODEC chip (tlv320aic3106) used on the LCDK. I could not find it anywhere on TI site?
2. Can you suggest a TI CODEC which much simpler than tlv320aic3106 but can measure ground symmetrical signals and has 24-bit resolution with 96 kHz sampling?
3. Does the C6748 chip have power down interrupt? We need to save value of some vital parameters during power down. We would add a large capacitor which would keep the CPU power 1-2 seconds longer than the main power so we would have time to save the parameters. Should we use an external power manager chip?
4. How can I write data into the internal flash memory? Is this possible or I have to use an external NOR flash chip?

Many thanks for your help!
Best regards,
Louis

Hi Mukul,
Thanks for answers. I will send a post to the CODEC forum.

Power: I could not find any power down interrupt in any manual of the C6748 (It has several). The LCDK uses TPS650250 power manager chip. This has a power fail output but it is connected to a test point only. I think power down interrupt is not implemented in the LCDK.

Writing to internal flash: Okay, I see now that the C6748 does not have internal flash, which is bad news.

Can you tell me how can I program the NAND flash of the LCDK board from CCS6? The Run >> Load >> Load program loads the *.out file into the DDR2 memory (I think) and CPU executes the program from the DDR2 RAM. The boot switches of the LCDK are set to boot from NAND flash but nothing happens on power on. Obviously my code was never loaded into the NAND flash memory.

Many thanks for your help.
Best regards,
Louis