EMIAF speed

Hi Mike,

What is your CPU operating frequency and for EMIFA module ?

By default, CPU would running at 300MHz and EMIFA will be 25MHz through gel file.

Set_Core_300MHz() {
    device_PLL0(0,24,1,0,1,11,5);
    GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:25MHz\n","Output",1,1,1);
}

Yes, this is what comes on the Console window at Debug startup --

C674X_0: Output:     Target Connected.
C674X_0: Output:     ---------------------------------------------
C674X_0: Output:     Memory Map Cleared.
C674X_0: Output:     ---------------------------------------------
C674X_0: Output:     Memory Map Setup Complete.
C674X_0: Output:     ---------------------------------------------
C674X_0: Output:     PSC Enable Complete.
C674X_0: Output:     ---------------------------------------------
C674X_0: Output:     PLL0 init done for Core:300MHz, EMIFA:25MHz
C674X_0: Output:     DDR initialization is in progress....
C674X_0: Output:     PLL1 init done for DDR:150MHz
C674X_0: Output:     Using DDR2 settings
C674X_0: Output:     DDR2 init for 150 MHz is done
C674X_0: Output:     ---------------------------------------------

Hi Mike,

Then try to change the EMIFA module frequency.

EMIFA source the clock from SYSCLK3, we can the change the PLLDIV3 if need to increase the EMIFA module freq.

Ex:

/*
   CLKMODE -  0---->On Chip Oscilator  1---->External Oscilator
   PLL0_SYSCLK1 - Fixed ratio /1
   PLL0_SYSCLK2 - Fixed ratio /2
   PLL0_SYSCLK3 - Variable Divider (EMIFA)
   PLL0_SYSCLK4 - Fixed ratio /4
   PLL0_SYSCLK5 - Not used -- do nothing
   PLL0_SYSCLK6 - Fixed ratio /1
   PLL0_SYSCLK7 - Variable Divider (RMII)
******************************************************************************************************************************************************/
device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 )
*/

Set_Core_300MHz() {
//    device_PLL0(0,24,1,0,1,11,5);
    device_PLL0(0,24,1,0,1,3,5);
    GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:100MHz\n","Output",1,1,1);
}

Thanks, Titus, I changed the gel file to do this.

It did not make it go faster.

Also, I had  changed

SOC_PLLC_0_REGS+ PLLC_PLLDIV3

in the attached . c file.

Hi Mike,

You can measure the clock through CRO/DSO for SYSCLK3 via CLKOUT pin (OBSCLK divider) to confirm.

Please note that EMIFA could support up to 150MHz and not more than that.

Hi, Titus, I got SYSCLK3 to show up on Test Pt. 10 on my LCDK board.

It has a cycle time of about 18 nsec.  This is the same as EMA_CLK (J14, pin 42)

Here are some register values printed by the .c program (program is attached)

      (HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(5)) 0x11000000
        HWREG(SOC_EMIFA_0_REGS +  EMIFA_AWCC) 0x00550000
        HWREG(SOC_EMIFA_0_REGS +  EMIFA_CE3CFG) 0x00000001
        HWREG(SOC_SYSCFG_0_REGS +  SYSCFG0_CFGCHIP3) 0x0000ff00
      HWREG(SOC_PLLC_0_REGS+ PLLC_PLLDIV3 ) 0x00008003
      HWREG(SOC_PLLC_0_REGS+ PLLC_PLLDIV3 ) 0x00008005

Alack, the EMIFA rate is still slow, about 500ns/read. (faster than it was by 2x)

Even though the EW bits are 0, I tried 0 and 1 on EMA_WAIT1 (J14, pin34). This had no effect.

Please let me know what you think.

Thanks,

Mike

Hi Mike,

I would like to suggest to modify the gel file which I given in earlier post and probe the TP10 to measure the SYSCLK3 to know what is the exact frequency used for EMIFA.

Try to modify the gel file before loading the program and avoid doing PLL stuff in code.

I will help you for the PLL stuff in code when we confirm that EMIFA frequency is the cause, so before that try to modify the EMIFA freq through gel file.

You can refer to the following link.

http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/375299/1322264.aspx#1322264

Hi, Titus, I used the gel file to set PLLC_PLLDIV3 to several values.  This changed TP10

which is the same as EMA_CLK (J14, pin42).

I've attached a plot of read time as a ftn of EMA_CLK.  There seems

to be some 250 ns memory access time (latency) not related to PLLDIV3.

I think this is a memory transfer issue. (EMIFA to L2).  Please help me

understand this!

 I find that the simple loop in L2 ram

  unsigned int i,j;

  for (i = 0; i<100e6; i++){ j = i;}

takes about 4 sec = 40 ns/step.

Thanks,

Mike

Hi Mike,

If it is not a EMIFA clock problem then try to use EDMA for data transfers as current example has the support and EDMA gives much better performance for data transfer.

HI, Titus, is there posted code about combining EMIFA and EDMA?

Should I start with edmaTest.c or nandReadWrite.c? (examples/edma/ or

examples/nand/)  In edmaTest.c, to read from EMIFA, would I just set the source data

pointer to 0x6200 0000?

Thanks,

Mike