SDTIMR1 write to read command delay

Tobyn VanVeghten

Other Parts Discussed in Thread: OMAPL138

Greetings,

I am trying to figure out how to configure my SDTIMR1 and SDTIMR2 registers for the DDR controller.

SDTIMR1

1. For the T_WTR (wrtie to read command delay), my datasheet shows 1 tck (tck = 6 ns), so I get -0.1 for this value. Does that mean I should set T_WTR to 0?

SDTIMR2
1. T_XSNR (exit self refresh to a non-read command) and T_RTP (read to precharge delay): I cannot find these in my datasheet. What other names could these go by?

2. T_XP: I get 0 for this. (T_XP and T_CKE are both 1(tck cycle)). Is 0 valid?

3. T_CKE: I also get 0 for this. Is 0 valid?

I've attached the datasheet for my particular mDDR chip for reference. This is on the C6748 DSP.

Thanks,

Tobyn

T67M_512Mb_mobile_lpddr_sdram.pdf

over 9 years ago

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Hi Tobyn,

Please refer to the following Ti wiki for DDR timing parameter calculation.

http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

0 Shankari G over 9 years ago

TI__Mastermind 43955 points

Hi Tobyn,

I am not an expert in DDR, however I have some suggestion for you.

There is a BSL sample test code available for DDR used on OMAPl138 LCDK and OMAPL138 Logic PD EVM. The part number is "K4T1G164QF-BCF8". ( samsung)

For that respective DDR "K4T1G164QF-BCF8", the timing parameter configuration is given below which is extracted from the BSL test code.

// Please note that this code is not the configuration for your DDR from Micron.

 // config ddr timing.
   DDR->DDRPHYCTL1 = 0x000000C4;
   DDR->SDCR = 0x0893C622;
   DDR->SDCR &= ((DDR->SDCR & 0xFF0FFFFF) | 0x00800000);
   DDR->SDCR = ((DDR->SDCR & 0xFF0FFFFF) | 0x02000000);
   DDR->SDCR &= (~0x00008000);
   
   DDR->SDTIMR1 = 0x20923A89;
   DDR->SDTIMR2 = 0x0015C720;
   DDR->SDCR2 = 0x0;
   DDR->SDRCR = 0x00000492;
   
   // set ddr2 to sync reset.
   SETBIT(DDR->SDRCR, 0xC0000000);
   
   // sync reset the ddr clock.
   EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_SYNCRESET);
   
   // enable the clock.
   EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_EMIF3A, PSC_ENABLE);
   
   // disable self refresh.
   CLRBIT(DDR->SDRCR, 0xC0000000);

Please refer to the data sheet and the timing configuration of the DDR used and co-relate / understand it . This will ease up or exercise the work when you refer to your original DDR datatsheet.

Meanwhile I will also look into it and get back.

Regards,

Shankari

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SDTIMR1 write to read command delay