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Doubt about Rounding Mode for TMS320C6000 CPU

Dear All,

I would like to clear a doubt regarding to the floating-point rounding mode for this processor.

Reading the documentation I realized that:

FADCR - Floating-point adder configuration register

Rmode .L2 - Value 00: Round toward nearest representable floating-point number

Rmode .L1 - Value 00: Round toward nearest even representable floating-point number

FAUCR - Floating-point auxiliary configuration register

There are no field for rounding mode.

FMCR - Floating-point multiplier configuration register

Rmode .M2 - Value 00: Round toward nearest representable floating-point number

Rmode .M1 - Value 00: Round toward nearest representable floating-point number

Doubts:

1) For FADCR - Rmode .L2: What happnes when a tie occurs? The rounding mode ties to even or away from zero?

2) For FAUCR: How can I set the rounding mode for this register?

3) For FMCR, both M1 and M2: What happnes when a tie occurs? The rounding mode ties to even or away from zero?

Thanks,

Lucas

  • Hi,

    Thanks for your post.

    These are the control file extensions (FADCR, FAUCR, FMCR) and you need to use the cregister keyword to access these registers through setting trial values and experimenting based on your clarification mentioned above regarding floating-point rounding mode. To access registers which is described in compiler user guide below and based on that, you could evaluate the checks raised by you which would clarify hopefully.

    http://www.ti.com/lit/ug/spru187v/spru187v.pdf

    Thanks & regards,

    Sivaraj K

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  • Dear Sivaraj,

    Thank you for your post, however I really expected a much more clear answer.

    I believe that I do not need to " trial values and experimenting". The TI should have it well-documented and the behavior of the processor should be known before execution.

    Please, could you confirm with your colleagues what is the specific answer of my question?

    I just want to know the rounding mode, in case of tie, if it goes to even or away from zero, as described by the IEEE 754 Standard.

  • Lucas,

    You have not specified a DSP core. The C6000 started as fixed-point only, then we added native floating point. I doubt the answers will vary from one family to the next, but it is not easy to be clear.

    The C6713B datasheet, for example, specifies that it implements IEEE 754 single- and double-precision floating point. We do not replicate the IEEE documentation, so you are referred to that specification for more information.

    Does the IEEE 754 specification address your question adequately?

    Regards,
    RandyP