EDMA3 LLD basic questions

Hi,

Thanks for your post.

All my answers would refer the appropriate sections in the C6748 TRM below:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

To answer #1,

Unlike DMA, QDMA is not event /manual/chain triggered instead it is auto/link triggered. A QDMA transfer will be triggered when a CPU/EDMA3  writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a specific QDMA channel (link triggered).

QDMA channels are typically for cases where a single event will accomplish a complete transfer since the

CPU/EDMA3 would reprogram some portion of the QDMA PaRAM set in order to retrigger the channel. Usually QDMA transfer are programmed with CCNT = 1 for AB-synchronized transfers where CCNT number of TRs can be expected for ACNT × BCNT bytes each. For more details, please refer Table 16-4 & Section 16.2.4.3 in the TRM above.

Each DMA channel and QDMA channel can be independently programmed to map to a specific queue using

the DMA queue number register n (DMAQNUMn) and the QDMA channel queue number register

(QDMANUM) and the mapping of DMA/QDMA channels is critical to achieving the desired performance level

for the EDMA. For more insight, please refer section 16.2.10 in TRM

To answer #2,

In the code, there would be obviour mapping between unique edma instances and appropriate DMA/QDMA channels. Please walk through the code end to end as you are not allowed to request a channel from an unmapped edma handle since it all mapped one to one.

To answer #3,

There is nothing like "link" channel to request and have only DMA/QDMA channels to request where as QDMA transfers requests can be link triggered to reload/update the non-null linked PaRAM sets for subsequent transfers. Actually, there is one to one mapping between DMA channel numbers and the PaRAM sets which are fixed and cannot be violated. Please refer Table 16-5 in TRM but the mapping between the QDMA channels and the PaRAM sets can be programmed as per our choice in the QDMA channel n mapping register (QCHMAPn) in the EDMA3CC and the QDMA channels can be mapped to any of the PaRAM sets in the PaRAM memory map. But, by default, QDMA channels are mapped to PaRAM set 0. Please refer Figure 16-10 for QCHMAP & section 16.2.6.2 for more details.

To answer #4,

By default, there is a one-to-one mapping between the queues and transfer controllers. So, the TRs associated with events in Q0 get submitted to TC0 and likewise, the TRs associated with events in Q1 will be submitted to TC1 respectively. An event that wins prioritization against other DMA/QDMA pending events would be placed at the end of the appropriate event queue. Always, a lower numbered queue has a higher dequeuing priority then a higher numbered queue. Please refer section 16.2.10 Event queue in TRM. So, each edma handle instance would be mapped to specific event queue based on event prioritized requests from different peripherals/external hardware which will not allow handle instance 1 to assign it to event queue 0.

To answer #5,

In order to run the SYSBIOS tasks through edma3 LLD calls, it is mandatory for BIOS to run

To answer #6,

Yes, it is possible through ping ponb buffer mechanism which would transfer 2 bytes one at a time until it reaches the full buffer capacity and then it interrupts once it completes the buffer. This is the approach used in EDMA LLD and you have the test code for dma ping pong buffer apporach.

BCNT reload (BCNTRLD) is the count value used to reload BCNT when BCNT decrements to 0 which is only applicable for A-synchronized transfers. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately and BCNTRLD is not used. For details, please refer section 16.2.3.2.7 & see Table 16-3 for parameter updates in EDMA3CC in TRM for a non null PaRAM set.

The destination (Dst) FIFO register set stores the context for the DMA

transfer request(s) currently in progress or pending in the write controller and the data FIFO holds temporary in-flight data. The source peripheral's read data is stored in the data FIFO and subsequently written to the destination peripheral/end point by the write controller. For more details on FIFO mode usage in EDMA3, please refer section 16.2.1.2 in TRM

Thanks & regards,

Sivaraj K

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i am asking almost entirely about the LLD, i read over the edma section in that document so i feel i have a fair understanding about the internals. i am asking about how the LLD works which is an abstraction and not a completely obvious 1 to 1 comparison to that document.  and to clear things up question 1 is the only question where i ask about qdma, the rest of the questions are referring to regular DMA channels. sorry if that was not clear.

1) I understand the qdma channels use a trigger word and are not configured with the same setup as the normal DMA channels.  my question was if the qdma does a true AB transfer because the code in the example makes it seem like i have to do bcnt iterations of acnt transfers to complete the entire transfer. i was also asking why when i request any channel from the lld it gives me channel 160. none of this was answered

2) my question was why would i have an error when i request a channel from handle 1. i am using the input of "request any channel" from this handle and i am getting error -139. i have tried it using multiple queues.  is there something special required to request any channel from the second instance of the edma? what does error -139 mean? i don't see any listing of error return codes in the documentation.

3) in order to get a "link channel" or a free param set you have to "request a channel" with a "channel any link" param. i am referring to it as the LLD refers to it, as a channel. i am asking if my interpretation of the LLD is correct. i understand there is a direct mapping of some of the channels to PARAM sets but i refer you to the same document page 500 where there are 32 channels per instance but 128 param sets. obviously 96 of the param sets are not associated with a live channel. looking at the documents helps me NOT AT ALL as to understanding how the LLD handles the param sets and channels.

4) so is my issue that i am referring to the wrong queue when i request a channel from instance 1? i see instance 1 has 1 queue.  is that queue, since it belongs only to instance 1, referred to as queue 0 or because it is the 3rd queue in the whole of the edma it is referred to as queue 2? when working with instance 1, assuming i can ever request a channel from it, what should i put for the queue, 0 or 2?

5) ok so i can only call the LLD when sysybios starts. however can i run any of the routines from non-task threads? can i makes calls in a Hwi or a Swi? that was not answered

6) thanks for letting me know it is possible but i am more asking for help about how it is possible.  what is the trick to do a single read at a time of 2 bytes until a buffer length is reached.  i didn't see the ping pong test in the example code ( might i have just overlooked it when trying to figure out how this thing works ) so i will look at the example and see if i can figure it out. however, i would still like an english explanation since most of the time the example code is severely under-commented and i would hate to misinterpret or assume something based on the example code which might not apply to my project. if it is too long to explain then i will just try to work out the example.

and i have read the definitions of the bcntrld and fifo mode but the definitions are not helping me understand what they are actually used for (situations) and if they play any part in getting the mcbsp process to work as i described before.

Hi Cobsonchael,

Please refer to the following link.

http://processors.wiki.ti.com/images/5/5e/EDMA3_LLD.pdf

edma3_lld_02_11_10_09/examples/edma3_driver/src/qdma_test.c
edma3_lld_02_11_10_09/examples/edma3_driver/src/main.c.

2) the 6748 seems to have 2 instances of the EDMA3 installed on it. in the example code they have an array for the edma handle and call edma3init for both of the instances. i did the same thing and no errors. my issue happens when i request a channel using hdma[1] instead of hdma[0]. i get error -139 every time. is there some trick to requesting a channel from handle 1 instead of using handle 0?

Have you initialized the EDMA3 instance 1 ?

edma3init(1, &edmaResult);

2) my question was why would i have an error when i request a channel from handle 1. i am using the input of "request any channel" from this handle and i am getting error -139. i have tried it using multiple queues. is there something special required to request any channel from the second instance of the edma? what does error -139 mean? i don't see any listing of error return codes in the documentation.

I've searched error code in source but not able to find.
Do you have emulator with you ?
If do so, do step by step debugging and findout the line which could cause the error.
It will assign some definitions to the results like below.

result = EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS;

What program are you trying ?

Install MCSDK for OMAPL138 and you could get PDK with some MCASP examples which is used EDMA stuff.

pdk_OMAPL138_1_01_00_02/packages/ti/drv/mcasp/src/mcasp_edma.c

1) I understand the qdma channels use a trigger word and are not configured with the same setup as the normal DMA channels. my question was if the qdma does a true AB transfer because the code in the example makes it seem like i have to do bcnt iterations of acnt transfers to complete the entire transfer. i was also asking why when i request any channel from the lld it gives me channel 160. none of this was answered

It should give 1 to 8 for QDMA.
Please ensure that you are configured QDMA as below.
edma3_lld_02_11_10_09/examples/edma3_driver/src/qdma_test.c

http://processors.wiki.ti.com/index.php/MCSDK_OMAPL138_User_Guide_Chapter_Exploring#Low_Level_Drivers_.28LLDs.29

i have looked over that EDMA_LLD.pdf document but it is dated and helps to an extent but does not answer my questions.

i have initialized the second handle before i request a channel. i do have an emulator and i am running CCSv5.5, unless you mean which example program i am using in which case i am not using an example program.

i had to move to a different project so i will have to look at this stuff when i get put on this project again.

Hi Cobsonchael,

Thanks for your update.

Instead of using legacy SDK's and dependant EDMALLD's, we would recommend you to install MCSDK for OMAPL138 and you could get PDK with some MCASP audio sample example which uses EDMA stuff which Titus had already suggested in the above post.

MCSDK would support both SYS/BIOS RTOS and Linux OS for OMAP-L138 LCDK platform and to install the latest MCSDK product release, please refer the below link:

http://www.ti.com/tool/bioslinuxmcsdk

To get started with MCSDK, please refer the below MCSDK user guide:

http://processors.wiki.ti.com/index.php/MCSDK_User_Guide_for_OMAPL138

Thanks & regards,

Sivaraj K

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