TMS320C6727 PLL

Hi Mahima,
How did run this code ie through flash or CCS IDE ?
Have you tried to debug the code through CCS and which line cause the problem ?
What are the difference you have on custom board related to DDR,flash etc.,?
Able to run any program on custom board ?
Are you facing problem only in PLL example ?

Hi Titus,

Thanks for your reply.

I run this code through CCS v5.0 .  I tried to run code step by step and it got stuck on this line

if (hwSetup->pllcMode == CSL_PLLC_PLLCSR_PLLEN_PLL) {

/* Set PLLEN = 1 */

CSL_FINS (hPllc->regs->PLLCSR, PLLC_PLLCSR_PLLEN,              ----------------- stuck on this line

CSL_PLLC_PLLCSR_PLLEN_PLL);

}

It is not going forward.

The interface schematic design is taken from GC5325 evaluation Board from TI.

I was able to run EMIF example .

Regards

Mahima Satsangi

I have attached the image of CCS software

Kindly look into this

Kindly look into this problem

Hi Mahima,
Could you share the EVM board and custom board's processor details (markings on the processor).
What are the difference you have on custom board related to DDR,flash etc.,?
Able to run any program on custom board without changing the PLL ?
You can also use PLL code from gel file of C6727.

Hi,

The details are given below :

DSP Weuffen C6727 EVM Board processor details - TMS320C6727BZDH
CI2-07ACZQW GI
Custom Board processor details - TMS320C6727BZDH
CI2-32A6EZW GI

I am able to run PLL in bypass mode.

I am not able to use the GEL file of C6727 EVM board . It is giving Error

"
C672X_0: GEL Output: PLL_CSR &= EN
C672X_0: GEL Output: PLL_CSR |= RST
C672X_0: GEL Output: PLL_DIV0
C672X_0: GEL Output: PLL_M
C672X_0: GEL Output: PLL_CSR &= RST
C672X_0: GEL Output: PLL_CSR |= EN
C672X_0: GEL Output: SDTIMER
C672X_0: GEL Output: SDSRETR
C672X_0: GEL Output: SDRCR
C672X_0: GEL Output: SDCR
C672X_0: GEL Output: A1CR
C672X_0: GEL Output: GEL StartUp Complete.
C672X_0: Trouble Reading Register CSR: (Error -1060 @ 0x0) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.872.0)
C672X_0: Trouble Reading Register CSR: (Error -1060 @ 0x0) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.872.0)

"

So I have tried connecting without GEL file.
In my earlier post, I have shown where am i getting error . I am not able to run in PLL mode ( PLLEN = 1).

The interface schematic design is taken from GC5325 evaluation Board from TI.

Kindly help me to sort out this problem.

Regards

Mahima Satsangi

What emulator are you using ?
Try to use adaptive frequency in emulator settings and then try to load gel file.
processors.wiki.ti.com/.../XDS100

I am using Blackhawk USB560 v2 System Trace
Part #: BH-USB-560v2

With setting JTAG TCLK Frequency - "Adaptive without any limit at all"
I am getting error

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\cdot\AppData\Local\.TI\693494126\
0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Oct 3 2012'.
The library build time was '22:14:17'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-507' (0xfffffe05).
The title is 'SC_ERR_TEST_INVERTER'.

The explanation is:
The user selected asynchronous adaptve frequency failed the scan-path test.
The utility or debugger requested the JTAG controller and cable,
that generate the JTAG clock, to use a user selected feature or
algorithm. The built-in scan-path reliability test has failed.
This indicates that the JTAG controller and its cable cannot reliably
communicate with the target system using that feature or algorithm.

[End]

Hi,

On Evaluation Board, One Flash Memory of 4MB is used
We dont have any flash memory on our board

Related to RAM
On Evaluation Board, one RAM is there whose size is 128MB - DQM0,1,2,3 are used for Bank selection
EM_CS0 is for Chip select

On Custom Board, two RAM of 128MB are there -
1st RAM EM_LDQM1_DQM0 is used for Bank selection
EM_CS0 is for Chip select
2nd RAM EM_LDQM1_DQM1 is used for Bank selection
EM_CS2 is for Chip select

EMIF.rtfHi,

I have tried EMIF example. Its working fine.

I have attached code .

Kindly look into this.

Regards

Mahima Satsangi