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Problem of LCD Raster when use O-3 optimization

Other Parts Discussed in Thread: TMS320C6748

when i  don't use any optimization, the lcd works well. When i use O-3 optimization, the screen will flicker . then i enable the cache of L1 and L2, it stops, but the image will be divided into a few parts and shows a falut position.

  • Hi,
    I've modified the optimization and not able see any neither flickering nor fault position.
    Could you please tell me which optimization used and how you enabled L1/L2 cache.
    Also, please try to do the same for linked libraries project (ex: drivers,platform etc.,)
  • i use O-3 optimization.
    CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);

    g_ptSysconfig0Reg->MSTPRI[2] &= 0x0fffffff;
    g_ptSysconfig0Reg->MSTPRI[2] |= 0x10000000;

    g_ptLcdcReg->RASTER_CTRL &= 0xfffffffe
    g_ptLcdcReg->LCD_STAT = 0x000003ff; // Clear
    // g_ptLcdcReg->LCD_CTRL = 0x00001601; //
    // g_ptLcdcReg->LCD_CTRL = 0x00000a01; //
    g_ptLcdcReg->LCD_CTRL = 0x00000c01; //

    // g_ptLcdcReg->RASTER_TIMING_0 = ((43)<<24)+((8)<<16)+((5)<<10)+(29<<4);
    // g_ptLcdcReg->RASTER_TIMING_1 = ((12)<<24)+((4)<<16)+((10)<<10)+0x10f;/*800*480*/
    // g_ptLcdcReg->RASTER_TIMING_0 = ((43)<<24)+((8)<<16)+((5)<<10)+(49<<4);
    // g_ptLcdcReg->RASTER_TIMING_1 = ((12)<<24)+((4)<<16)+((10)<<10)+0x1df;
    g_ptLcdcReg->RASTER_TIMING_0 = ((43)<<24)+((8)<<16)+((5)<<10)+(39<<4);
    g_ptLcdcReg->RASTER_TIMING_1 = ((12)<<24)+((4)<<16)+((10)<<10)+0x1df;

    g_ptLcdcReg->RASTER_TIMING_2 = 0x03000000;
    g_ptLcdcReg->RASTER_SUBPANEL = 0x0;
    g_ptLcdcReg->LCDDMA_CTRL = 0x00000540;//0x00000020; //先传低位
    // g_ptLcdcReg->LCDDMA_FB0_BASE = FRAMEBUF_BASE+0;//FRAMEBUF_BASE;
    g_ptLcdcReg->LCDDMA_FB0_BASE = FRAMEBUF_BASE;//(unsigned int)&lcdimage[0
    // g_ptLcdcReg->LCDDMA_FB0_CEILING = FRAMEBUF_BASE+32+480*272*2-2;
    // g_ptLcdcReg->LCDDMA_FB0_CEILING = FRAMEBUF_BASE+32+CN_LCD_SIZE_X*CN_LCD_SIZE_y*2-2;
    // g_ptLcdcReg->LCDDMA_FB0_CEILING = FRAMEBUF_BASE+32+800*480*2-2; //
    g_ptLcdcReg->LCDDMA_FB0_CEILING = FRAMEBUF_BASE+32+640*480*2-2; //
    g_ptLcdcReg->RASTER_CTRL = 0x00000080;//0x00000080;
    g_ptLcdcReg->RASTER_CTRL |= 0x00000001; // Enable controller


    lcd_point = (unsigned short *)0xC1A00020;//ddr
    then i use the lcd_point to update the data of lcd.
  • Hi,
    Are you using LCDK board or custom board ?
    Have you modified the code ?
    Could provide the screen shot of the optimization settings.

    I've tried the raster LCD code on my OMAPL138LCDK (DSP core) with -o3 optimization and working good.
  • i use my own boad of TMS320C6748. off course i change the code of lcd raster setting

    the lcd data points to ddr2 in a certain addr, i update the data every time. 

    here are the optimization setting.

    here is my cmd file of memory

    MEMORY
    {
    L2: o = 0x00800000 l = 0x00040000
    // share: o = 0x80000000 l = 0x00020000
    L1P: o = 0x00E00000 l = 0x00008000
    L1D: o = 0x00F00000 l = 0x00008000
    dsp_ddrii: o = 0xc2000000 l = 0x1000000
    }

    /* =========================================================================*
    * Specify the Sections Allocation into Memory *
    * =========================================================================*/
    SECTIONS
    {
    .cinit > dsp_ddrii /* Initialization Tables */
    .pinit > dsp_ddrii /* C++ Constructor Tables */
    .const > dsp_ddrii /* Constant Data */
    .switch > dsp_ddrii /* Jump Tables */
    .text:_c_int00 > 0xc2000000
    .text > dsp_ddrii /* Executable Code */

    // .stack > IRAM

    .bss > dsp_ddrii /* Global & Static Variables */
    .far > dsp_ddrii /* Far Global & Static Variables */
    .stack > dsp_ddrii /* Software System Stack */
    .sysmem > dsp_ddrii /* Dynamic Memory Allocation Area */

    .cio > dsp_ddrii /* C I/O Buffer */
    .vecs > dsp_ddrii /* Interrupt Vectors */
    }

  • Hi,
    Do you have LCDK board with you ?
    Have you tried the unmodified example code on LCDK board ?
    Have you modified the raster example code ?
  • i don't have lcdk board. actually, the code is almost the same as example. only if i use optimization , the problem will appear, other parts work well . I think it maybe the ddr setting.

    if i use cacheenable L2 and cacheenableMAR, the lcd will work well in debug ,but not in nor flash.