Hi everyone,
I'm currently designing a board with a C6747 DSP and an FPGA. The idea is to stream data between them using EMIF A in synchronous mode (the FPGA will mimic a SDRAM-like interface). The address lines won't be needed in the application, as the FPGA will be acting as a FIFO, outputting/receiving a sequential stream regardless of the requested address.
However, I do need some lines to allow the FPGA to interrupt the DSP. It would be convenient to reuse the EMIF A address lines for this purpose, as they also are GPIOs.
So, my question is: can I enable the EMIF A peripheral while at the same time setting up the PINMUX registers so that some address lines are selected as GPIOs?
Thanks,
- Dave