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How to set PLLDIV2 of PLL When using DSP/BIOS CLK Manager?

Sir,

Now  I am using c6726 DSP with DSP/BIOS and want to generate 1ms sytem ticks, 

RTI reference guide tells me RTI clock input(RTICLK) derived from SYSCLK2, 

PLLDIV1 is 0x00,when I set the PLLDIV2 to 0x01, the system ticks' period is 1ms,

when I set the PLLDIV2 to 0x03, the system ticks' period is 2ms.

According to my understanding, the PLLDIV2 value should be 0x03, SYSCLK2 equals to 1/4 of SYSCLK1.

So it's confusing,please tell me how to set PLLDV2 .

Steven

  • Hi,
    What is your SYSCLK1 frequency ?

    PLLM, PLLDIV0 and OSCIN ?


    According to my understanding, the PLLDIV2 value should be 0x03, SYSCLK2 equals to 1/4 of SYSCLK1.

    Edited:

    No, if you set 0x3h to PLLDIV2 register then you would get SYSCLK2 = PLLOUT/4

    PLLOUT is depends on PLLM and PLLDIV0.

    Please refer to the following PLL UG.

    www.ti.com/lit/pdf/spru879

  • Thanks for your reply.

    My SYSCLK1 frequency is 245.76MHz
  • OSCIN=24.576MHz
    PLLM=0x0a
    PLLDIV1=0x00

    So ,
    PLLOUT = 245.76
    SYSCLK1=245.76*1 = 245.76

    As mentioned above, when I set PLLDIV2=0x03, actual system tick period is 2m,
    when I change PLLDIV2 TO 0x01, actual system tick period is 1m.

    The follow is the CLK Manager setting.

    I am confused about the value of PLLDIV2, which should be 0x03  rather than 0x01. 

  • Then RTI module running at 61.44MHz when you set PLLDIV=0x3h.
    What is the value of "RTICPUC0" register ?
  • RTICPUC0=0x1
    RTIUDCP0=0x0000F000

    BTW, RTI Register is my duty to set or BIOS set it automatcially?

  • Then it seems correct behavior.
    61440 == 0xF000
    You can change the settings in DSP/BIOS clock manager setting as you above shown.
  • Hi Titus S.

    I have already set the CLK manager like above, and in order to check the system tick period,add a CLK object ' CLK0'

    within which I define a function FXN_F_Clk0. When the application running, define a breakpoint at the FXN_F_Clk0 funciton.

    First I enable the clock (Run->Clock->Enable), when the programme breaks in FXN_F_Clk0 funciton for the first time, I rest the 

    clock, Run continually the programme will breaks for the second time, The clock value is 491397.

    SYSCLK1 frequency is 245.76MHz, so the period of system ticks can be calculated like below,

    (1/245.76/1000/1000)*491397 = 2ms

    Picture 1. DSP CLOCKS

    OSCIN=24.576MHz
    PLLM=0x0a
    PLLDIV1=0x00 
    PLLDIV2=0X03

    Picutre 2. PLL Registers Setting.

    Picture 3. RTI Registers Setting.



    Theoretical system tick period = 1ms
    Actual system Ticks period = 2ms, 

    So the question still exists, please give me some suggestions.