• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 102 subscribers
  • Views 785 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6748 DMA to/from DDR doesn't work but OK to/from internal RAM

Mohamed Sharaf
Prodigy 180 points
Other Parts Discussed in Thread: OMAPL138

I have a problem DMA transfers to/from DDR. The DMA seems to timeout from time to time. I think it has something to do with caching, but I don't know where to look. I'd be great if someone guides me to where I should start.

I'm using the LCDK development kit.  So I'm ruling out  any issues with the DDR2 connection/wiring. 

  • 0
    TI__Guru** 116100 points
    Hi,
    Which example code are you using?
    Any TI code like starteware, CSL, quickCSL etc., or your own code?
    You can refer to the C6748/OMAPL138 starterware package for DMA transfer and cache example code.

    processors.wiki.ti.com/.../StarterWare
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 180 points

    Hi Titus,

    I'm integrating the starterware nand example in my application. At first, when the rx and tx buffers for a nand page reading or writing were in DDR2 the transfers didn't work at all. When I placed them inside the IRAM (like the starterware example) the transfers worked fine most of the time, but with DMA failures (due to the transfer timing out). Should I start by checking the DMA parameters or does it have something to do with caching or both?  

    Thanks,

  • 0 in reply to Mohamed Sharaf
    TI__Guru* 84110 points
    Mohamed,

    Use CCSv6 to look at the DDR2 memory immediately after the DMA transfer. You can use the L1 and L2 checkboxes to see what is in the memory through the cache view or through the non-cache view.

    If you have cache enabled for this region of DDR2, then the correct usage is to always invalidate that region of memory after a DMA write to the region and before reading from it using the DSP core.

    Regards,
    RandyP
  • 0 in reply to RandyP
    Prodigy 180 points

    Hi Randy P,

    Thanks for replying. I will try what you proposed. 

    I think my problem now is directly related to interrupts. I am trying to write into NAND inside an interrupt service routine. I think the EDMA isr isn't getting exectued and hence it times out. I still don't fully understand nested interrupts and how to configure interrupt priorities, I'll have to read more into the interrupt controller documentation. Thanks again.

    Regards,

    Mohamed