I have a design, the official TI DEMO reference and Tronlong development board, the use of DSP is TMS320C6748, kernel version 2.3.
USB using the USB0 channel.
In c6748 USB PHY, the FIFO size is set for 512Byte. Each transmission,write 512Byte bytes data to the FIFO, and then enable the txrdy. On the Tronlong development board, stable data transmission, the data rate for 7~8MB/s .But in my design of the board, only to send a few packets of data, and then there is a mistake, can not continue to send.
When an error occurs, check the PERI_TXCSR register value is 0x0003, indicating that the DSP program to write data to the PHY FIFO USB, and start the send, but did not send complete.
Using BusHound error DSP to show that the The can send a few packets of data, and then the USTS error state, the error code is 0xC0000011, the error code is device returned a transaction.
The FIFO size set for 512Byte. Every time you send, write 256Byte bytes of data into the FIFO, and enable the txrdy and on the Tronlong development board to data transmission is stable, but data rate is decreased to about 1.7MB/s. Using my board can also stabilize the transmission data, the rate is also about 1.7MB/s.
The test of several cases on the board I made
Case 1, if I set FIFO to 512Byte, write 512Byte to FIFO, and then start to send, this situation can only send a few packets of data.
Case 2, if I set the FIFO to 512Byte, every time the 256Byte to FIFO, and then start to send, this case can be stable transmission data.
Case 3, if I set FIFO to 64Byte, every time 64Byte to FIFO, and then start to send, this situation can only send a few packets of data.
Please help me analyze, why my board every time to send full FIFO data will be a mistake?
Why the rate of each transmission 256Byte to reduce so much, what is the speed of this situation?
