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C6747 GPIO problem

Hello!.  I am a new user of C6747 device.  When I manage GPIO pins as individual  outputs, I found a problem.  It is as follows.

I configured some GPIO pins as output and wrote 1 into  corresponding bits of  GPIO_CLR_DATAxx register to drive that pin low.  But I found other GPIO output pin was affected from this operation.

In more detail, first I drove  a GPIO pin low  using corresponding GPIO_CLR_DATAxx registers and after some cycles, drove it high using GPIO_SET_DATAxx  , and repeated these two operation like as  a SPI_CLK  to external memory.  At  a same time, I output a data through other GPIO pin of the same GPIO bank synchronously with former, like as SPIMO. But found the signal wave of the data differed from the driving and affected the like clock pin's state by oscilloscope measuring. 

After that, I changed GPIO_CLR_DATAxx and GPIO_SET_DATAxx operations with GPIO_OUT_DATAxx operations. Then this situation was disappeared and the result was normal. 

What's the reason?  

  • Hello,

    It is an expected behavior. You need to perform read-modify-write operation on GPIO_OUT_DATAxx register to take effect the changes on GPIO_CLR_DATAxx and GPIO_SET_DATAxx registers.

    Please go through section "20.2.6 Using a GPIO Signal as an Output" in device TRM for detailed explanation on this.

    www.ti.com/.../spruh91b.pdf

    Regards,
    Senthil

  • Senthil.
    Thanks for your attention.
    Do you mean that I must use GPIO_OUT_DATAxx to drive GPIO output pins,but not GPIO_SET_DATAxx and GPIO_CLR_DATAxx?
    I already read the spruh91b.pdf. It says " • Write a logic 1 to the bit in CLR_DATA associated with the desired GPIO signal(s) to be driven low. Bit
    positions in CLR_DATA containing logic 0 do not affect the state of the associated output signals."
    Is it wrong or under which configuration is it true?
    Regards.
  • Hello Suyon,

    Either you are driving the GPIO output high or low, you should follow the steps given in section 22.2.6.2.1 and/or 22.2.6.2.2. Without writing the OUTDATA register, you may get the desired output at physical GPIO pin.

    Please have a look into the Figure 22-1. GPIO Block Diagram. The physical pin is directly connected to the OUTDATA register and SETDATA/CLRDATA does not have direct connection to the physical pin. Hence the output state would flow from OUTDATA register to the physical pin.

    Regards,
    Senthil