I wonder if the C674x has any way to write large arrays without:
- fetching the target cacheline on write miss
- polluting the caches with data that won't be used for a while
Is there any way to do either or both of these, without using DMA engines?
Intel x86 CPUs have special SSE instructions which perform "non-temporal stores". These accomplish #2.
Another DSP I once programmed had a special instruction for allocating cachelines. This avoided a cache fetch on write misses (it was a copy-back cache), but it had to be used with care (it would trash the entire address range mapped by the cacheline).