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How to avoid polluting the cache, when writing large arrays?

I wonder if the C674x has any way to write large arrays without:

  1. fetching the target cacheline on write miss
  2. polluting the caches with data that won't be used for a while

Is there any way to do either or both of these, without using DMA engines?

Intel x86 CPUs have special SSE instructions which perform "non-temporal stores".  These accomplish #2.

Another DSP I once programmed had a special instruction for allocating cachelines.  This avoided a cache fetch on write misses (it was a copy-back cache), but it had to be used with care (it would trash the entire address range mapped by the cacheline).

  • There's not a feature specifically for doing this.  The L2 cache is a read-write-allocate cache, so allocating a line into the cache is unavoidable on a write miss.  It might be worth noting that the L1D on the other hand is actually only read-allocate.  So for example if you disabled the L2 cache and were using only L1 cache, then you would get the behavior you mentioned.  Specifically, write misses would NOT cause the line to be allocated into the L1 cache.  Additionally you would still have the benefit of a write buffer (e.g. for pipelining, write merging, etc.).

  • Thanks. I guess EDMA is the way to do it. I hate that it costs us half our L2 Cache, among other things.