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C6743 boot from NAND 8-bit

Anton Evstafiev
Prodigy 160 points

Hi,

When I'm trying to boot C6743 from NAND 8-bit, it does't work.

NAND device is in supported NAND devices list (ID 0x75) - NAND256W3A2BZA6E.

I'm using working *.out file, AISgen utility, and application tested on UART0 boot.

The only change I made is selecting NAND 8-bit instead UART0.

I have read sprabb1c and (as was recommended in my previous post - spra04g).

I'm burning  *.bin file to the NAND starting from block 1 page 0.

NAND is connected to DSP according sprabb1c:

NAND Flash should be connected to EMA_CS[3] of the EMIFA peripheral. The ALE and CLE pins of the
NAND device should be connected to the EMA_A[1] and EMA_A[2] pins of the EMIFA peripheral,
respectively.

My program do not use first 16kB L2 RAM as recommended in sprabb1c:

Memory Usage: The bootloader uses 16 KB of DSP L2 RAM starting from 0x11800000 for multiple
purposes. This memory should not be used by any initialized section of the user application.

It should be noted that on C6743 the memory map slightly differ from C6747: L2 RAM resides addresses from 0x11820000 - 0x1183FFFF,

as described in sprs565d.

Test bytes of each page is 0xFF, 10 ECC bytes are programmed.

The access to the NAND is performed, that I can see on oscilloscope attached to corresponding pins.

What may be wrong?

Thanks in advance for any ideas!

  • 0
    Prodigy 160 points

    Hi all!

    The problem was in burning image to NAND.

    My experiment reveals that spare bytes of each NAND page should be programmed like this:

    Test bytes (0 - 5): all 0xFF!

    ECC bytes (6 - 15): 10 8-bits values (so called, 4-bit ECC -  Reed-Solomon error correcting code)

    To burning NAND I have used llc_nand driver from pspdrivers_01_30_00_05.

    The function LLC_nandWritePage writes in test bytes not all FFs, only first two bytes are FFs. The bytes 2-5 are programmed by logicalBlock and logicalPage values.

    To fix the problem I set logicalBlock=0xFFFFFFFFu and logicalPage=0xFFu in LLC_nandSpareArea structure (one of the input parameters) for any call of the function LLC_nandWritePage

    To ensure that bin executable is correct I've been using UART host application and boot from UART0.

    That's allow me to prepare working AIS-based binary file.

    Many thanks for TI's hardware developers - there are no cases when hardware and firmware was mulfunction!

    In fact, when you faced with any issue on TI DSP you may be sure the problem is in software. You should check MMR registers contens and ensure proper values.

  • 0
    Prodigy 160 points
    Additional question:
    In order to keep application data uncorrupted by NAND8 boot loader Should I create special data section 16 kB at the beginning of L2 memory? The application should use SYS/BIOS and SDR SDRAM attached via EMIFB? What is the best way to do this on CCSv5 and SYS/BIOS (bios_6_35_04_50, xdctools_3_25_03_72) ?
  • 0 in reply to Anton Evstafiev
    TI__Guru** 116100 points
    Dear Anton,
    Did you refer the NANDwriter CCS project ?
    You can get the NANDWriter code from flash and boot utils package, there you can just configure the NAND to 8bit mode and then try.
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 160 points
    Titus S,

    Yes, I have seen the NANDwriter project but after I finished llc_nand integration into my project.

    Anyway, I need nand functionality in working project and some nand testing for board production, so that work is not meaningless.

    Thanks!
  • 0 in reply to Anton Evstafiev
    Prodigy 160 points

    One more question:

    Regarding boot time. AIS-generated binary file is about 100kB.

    Case 1:   Booting AIS w/o CRC checking. The boot time is approx. 160 ms

    Case 2:   Botting  AIS with crcCheckType = SECTION_CRC. The boot time is approx. 1000 ms

    Case 3:   CACHE L2 = 32kB plus L2 cacheable. The boot time is approx. 460 ms

    Case 4:   Added SDRAM area cacheable. The boot time is approx. 320 ms

    Case 5:   Set crcCheckType = SINGLE_CRC. The boot time still is approx. 320 ms

    Notes:  

    1. Sections are loaded to SDR SDRAM.

    2. crcCheckType = SINGLE_CRC has no difference

    3. With CRC checking the largest section loads with 120ms than 120 ms pause, then next section loaded followed by pause.

    Case 5 booting time seems to be acceptable.

    Though are there any ideas how to improve booting time? It seems that CRC calculation spends too large time.

    The ini file for HexAIS.exe is as follows:

    ; General settings that can be overwritten in the host code
; that calls the AISGen library.
[General]

; Can be 8 or 16 - used in emifa
busWidth = 8            

; EMIFA,NONE
; EMIFA required for NOR boot modes, along with busWidth field
BootMode = NONE

; NO_CRC,SECTION_CRC,SINGLE_CRC
crcCheckType = SECTION_CRC


; This section should be used in place of PLL0CONFIG when
; the I2C, SPI, or UART modes are being used.  This ensures that 
; the system PLL and the peripheral's clocks are changed together.
; See PLL0CONFIG section for the format of the PLL0CFG fields.
; See PERIPHCLKCFG section for the format of the CLKCFG field.
;           |------24|------16|-------8|-------0|
; PLLCFG0:  |    PLLM| POSTDIV| PLLDIV3| PLLDIV5|
; PLLCFG1:  | CLKMODE| PLLDIV7|PLL_LOCK_TIME_CNT|
; Use with caution. The format of the PERIPHCLKCFG field 
; is as follows:
; SPI:        |------24|------16|-------8|-------0|
;             |           RSVD           |PRESCALE|
;
; I2C:        |------24|------16|-------8|-------0|
;             |  RSVD  |PRESCALE|  CLKL  |  CLKH  |
;
; UART:       |------24|------16|-------8|-------0|
;             | RSVD   |  OSR   |  DLH   |  DLL   |
[PLLANDCLOCKCONFIG]
PLLCFG0 = 0x18010205
PLLCFG1 = 0x010501B9
PERIPHCLKCFG = 0x00010064

; [AIS_Set]
; TYPE=Type field for AIS SET/BOOT_TABLE command
; ADDRESS=Address field for AIS SET/BOOT_TABLE command
; DATA=Data field for AIS SET/BOOT_TABLE command
; SLEEP=Sleep field for AIS SET/BOOT_TABLE command
; Enable PLL_DIV4.5 and connect EMIFB_CLK to PLL_DIV4.5
[AIS_Set]
TYPE    = 0x00020004 
ADDRESS = 0x01C14188 
DATA    = 0x00000005  
SLEEP   = 0x00000000

; This section allows setting of a single PINMUX register.
; This section can be included multiple times to allow setting
; as many PINMUX registers as needed.
;         |------24|------16|-------8|-------0|
; REGNUM: |              regNum               |
; MASK:   |               mask                |
; VALUE:  |              value                |
[PINMUX]
REGNUM = 0
MASK   = 0xFFFFFFFF
VALUE  = 0x11112181

[PINMUX]
REGNUM = 1
MASK   = 0xFFFFFFFF
VALUE  = 0x11111111

[PINMUX]
REGNUM = 2
MASK   = 0xFFFFFFFF
VALUE  = 0x01111111

[PINMUX]
REGNUM = 5
MASK   = 0xFFFFFFFF
VALUE  = 0x11111110

[PINMUX]
REGNUM = 6
MASK   = 0xFFFFFFFF
VALUE  = 0x11111111

[PINMUX]
REGNUM = 7
MASK   = 0x00000FFF
VALUE  = 0x00000111


; This section should be used to setup the power state of modules
; of the two PSCs.  This section can be included multiple times to
; allow the configuration of any or all of the device modules.
;           |------24|------16|-------8|-------0|
; LPSCCFG:  | PSCNUM | MODULE |   PD   | STATE  |

; PSC1.6 EMIFB
[PSCCONFIG]
LPSCCFG = 0x01060003

; PSC1.3: GPIO
[PSCCONFIG]
LPSCCFG = 0x01030003


; Enable sequential read mode for boot modes that support it.
; Does not impact boot modes that don't use it.
;[AIS_SeqReadEnable]=FALSE


; This section can be used to configure EMIFB registers
; for starting the SDR SDRAM interface. 
;            |------24|------16|-------8|-------0|
; SDCR:      |              SDCR                 |
; SDTIMR:    |              SDTIMR               |
; SDTIMR2:   |              SDTIMR2              |
; SDRCR:     |              SDRCR                |
[EMIF3SDRAM]
SDCR     = 0x00014621
SDTIMR   = 0x0E9129C8
SDTIMR2  = 0x70080005
SDRCR    = 0x00000410

; This section can be used to configure the async chip selects
; of the EMIFA (CS2-CS5).  The fields required to do this
; are given below.
;           |------24|------16|-------8|-------0|
; A1CR:     |                A1CR               |
; A2CR:     |                A2CR               |
; A3CR:     |                A3CR               |
; A4CR:     |                A4CR               |
;[EMIF25ASYNC]
;A1CR = 0x3FFFFFFC
;A2CR = 0x70C98640
;A3CR = 0x3FFFFFFC
;A4CR = 0x3FFFFFFC


; Enable GPIO4.0
[PINMUX]
REGNUM = 12
MASK   = 0x000F0000
VALUE  = 0x00080000

; Set GPIO.DIR45.0 = 1 - to output
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01E26060
DATA    = 0xFFFFFFFE 
SLEEP   = 0x00000000

; Set GPIO.SET_DATA45.0 = 1
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01E26068
DATA    = 0x00000001 
SLEEP   = 0x00000000

; Set GPIO.SET_DATA45.0 = 0
;[AIS_Set]
;TYPE    = 0x00000002
;ADDRESS = 0x01E2606C
;DATA    = 0x00000001 
;SLEEP   = 0x00000000

; Set L2CFG to L2 CACHE_SIZE = 32kB
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01840000
DATA    = 0x01010001
SLEEP   = 0x00000000

; Set MAR0 (L2 RAM)
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01848000
DATA    = 0x00000001
SLEEP   = 0x00000000

; Set MAR192 (SDRAM 0xC0000000 .. 0xC0FFFFFFF)
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01848300
DATA    = 0x00000001
SLEEP   = 0x00000000

; Set MAR193 (SDRAM 0xC1000000 .. 0xC1FFFFFFF)
[AIS_Set]
TYPE    = 0x00000002
ADDRESS = 0x01848304
DATA    = 0x00000001
SLEEP   = 0x00000000

; No Params required - simply include this section for the fast boot function to be called
;[FASTBOOT]