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Cycle count for instruction execution on C6748 LCDK

Steven Popovich47
Prodigy 20 points
Other Parts Discussed in Thread: TMS320C6748

I'm running a TMS320C6748 LCDK EVM and have noticed code seems exceptionally slow to run.  At startup, a GEL file for the LCDK is being loaded and claims success at setting the speed to 300MHz.  I have also confirmed the clock in CCS along along with the test referenced from 

https://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/54812

that the DSP speed is indeed at 300MHz.  However, when I single step through the assembly code, it takes 6 clock cycles for each and every instruction, no matter where in memory the code or data is located.  For example, a NOP 3 instruction requires 18 clock cycles.  Shouldn't code based internally referencing internal data be faster than this?  Is there some kind of slow mode my unit could be running in?

I appreciate any insights on how this works!

  • 0
    Prodigy 20 points
    I should add - it's 6 cycles for each instruction step. That is, when stepping via ctrl-shift-F5.
  • 0 in reply to Steven Popovich47
    TI__Guru* 84110 points
    Steven,

    Welcome to the forum!

    Measuring cycles when single-stepping is not a good way to evaluate performance. The best method is to locate and use the TimeStamp Counter TSC that consists of two 32-bit registers, TSCL and TSCH. You can search this forum for TSCH to find code examples and discussions of using it for timing measurements.

    Start the TSC, then read it just before starting a sequence of code, then read it after that sequence of code and subtract the two readings. For best accuracy, you will want to account for the cycles used to read the TSC, which is also discussed in previous forum threads.

    You will set a breakpoint just after taking the difference, then run to that breakpoint to get a measurement.

    The C6000 instruction set is too complex to get a meaningful number from single-stepping.

    Regards,
    RandyP