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C6746 Megamodule Power down

Cesar Aguilar
Prodigy 230 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

In my realtime system, the C6746 DSP is loaded 60% consistently (3ms out of 5). Therefore, I would like to power down the megamodule the remaining 2ms for current drain reasons. I am trying to use the C674X Megamodule power down instructions described in 9.2.5 in sprufk5a.pdf, but it is not working. In order to do this, I am running the following lines in the background task (no RTOS) whenever the mainloop waits for an interrupt to occur with new data to start processing:

HWREG(PDCCMD_REGS) |= 0x00010000;  //PDCCMD_REGS defined as 0x01810000
asm("IDLE"); 

There are 2 interrupts in the system that are enabled at power up and never again disabled or enabled. I want the DSP to wake up if any of the 2 interrupts fires off. That is the reason why the interrupts are not enabled again before the asm instruction.

HWREG(PDCCMD_REGS) is set to 0 in the context of any of the 2 interrupts to disable the power down feature.

My questions are:

1- Is there any step that I am missing here.

2- The document mentions that to change PDCCMD_REGS, the processor has to be in "Supervisor mode".  How do I put the C6746 in Supervisor mode?

3- The document mentions that this mechanism should be used only for "longer periods of time". Is 2ms considered a long period of time?

4-  Are there any examples on how to do this (in Starterware for example)?

  • 0
    TI__Guru** 116100 points
    Dear Cesar,
    Can you please refer this post ?
    e2e.ti.com/.../1044501

    A2) You have to unlock the KICK registers for supervisor mode.
    A3) I hope this timing is not sufficient (2ms).
    A4) We don't have such a examples from starterware.
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 230 points

    What do you mean on A3? Are you saying that 2 ms is not sufficient to use this mechanism?  So, why not?  What time ranges TI recommends to use it with?

    Thanks

    Cesar

  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 10 points
    I am working with Cesar on this issue. I checked the bit 6:7 of TSR register, and can make sure that it's in SUPERVISOR mode. After executing the below code, then I go to check the PWRD field of CSR register, it's still get 0, means NO power-down. but we expected to get 9h, means Power-down mode PD1, and wake by an enabled interrupt.
    HWREG(PDCCMD_REGS) |= 0x00010000; //PDCCMD_REGS defined as 0x01810000
    asm("IDLE");

    I also checked the PDCCMD register value, it's 0x00015555. the MEGPD bit has been changed to 1, but the 15:0 bit is not 0xFFFF by default. From the document, these 15:0 bits are reserved and should always read as 1, but here I read these bits as 0x5555, I am not sure whether there's something wrong.
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 230 points
    What do you mean on A3?
    Are you saying that 2 ms is not sufficient to use this mechanism?
    So, why not?
    What time ranges does TI recommend to use it with?
    If this mechanism cannot be used, what does TI recommend to use instead to save power for 2ms?

    Thanks

    Cesar
  • 0 in reply to Cesar Aguilar
    TI__Genius 12015 points
    Cesar,
    I'm checking around for archived information on this and will post here if/when we find something. In the meantime, have you considered measuring the latencies to enter/exit the low power modes using an example on a TI EVM board? I realize that your application is not using SYSBIOS, but the latency measurements should be similar in both scenarios. There is an example based on the SYS/BIOS Power module at this link: processors.wiki.ti.com/.../Power_Module_for_C6748_and_OMAP-L138

    -Ruben
  • 0 in reply to rperezti
    TI__Guru* 78365 points
    Hi Cesar, Hongyu
    Is this issue still open?

    I am not sure if this can be an issue, but can you try to add a space in your idle instruction

    instead
    HWREG(PDCCMD_REGS) |= 0x00010000; //PDCCMD_REGS defined as 0x01810000
    asm("IDLE");

    do
    HWREG(PDCCMD_REGS) |= 0x00010000; //PDCCMD_REGS defined as 0x01810000
    asm(" IDLE");


    You can also put a bunch of nop instructions after your IDLE and see if during single stepping the CPU hits the NOPs after IDLE instruction?

    In terms of pure hardware latency to wake up from megamodule sleep mode is in the order of ~300 cpu cycles, this number does not include additional over head and latencies attributed to wake up ISR, other software and OS related overheads

    I would recommend looking at the link Ruben provided
    if you look at the PWRM package files under SYSBIOS

    \packages\ti\sysbios\family\c674\
    you will find a bunch of files that are bare metal and can be used as a reference for deep sleep, frequency scaling etc. Although I don't see the megamodule idle supported.

    Please also make sure you are looking at the power consumption summary for the device to see the ROI on power savings on megamodule idle vs frequency scaling etc.

    Hope this helps.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Prodigy 230 points
    Hi Mukul

    The space was the issue. If the space is not added, the idle instruction is not executed.

    Thanks

    Cesar
  • 0 in reply to Cesar Aguilar
    TI__Guru** 116100 points
    Sounds good.
    Thanks Cesar for your confirmation.