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C6748 nReset IPU - really implemented in silicon?

Other Parts Discussed in Thread: TMS320C6748

Hello TI,

In Table 3-5 on page 27 of sprs590f, the nReset pin (K14) is specified to feature an internal pull-up (IPU) to Power Group B, non-configurable. However, I cannot seem to measure / verify this functionality in real silicon, at least none complying with the 70uA - 310uA input current range specified in Section 5.5 on pg. 79 of the same datasheet.

Please confirm:

1) that IPU functionality is indeed implemented on the nReset pin of the C6748 (and the L138)

2) what the input current specification for this pin in the current Silicon Revision (2.3) would be.

Thanks,

Bernhard

  • We are working on your post.
    Thanks for your patience.
  • Bernhard,

    1. Yes, internal pull up is implemented on the nRESET pin.

    2. There is no change in the input current with respect to the silicon revision. The input current specification in the datasheet applies to the silicon revision 2.3 as well.

    What is the voltage you are seeing at the RESET pin ?

    Do you have any external pull up resistor on RESET pin in your design ? If so, what is the resistance value ?

    Regards,
    Senthil
  • Hello Senthil,

    We have a design with a 100K pull-up connected to an open-drain Supervisor. There is no evidence of an internal pull-up in the DSP.

    Loading the pin with the following pull-down resistors on the nReset pin (additional to the 100K external pull-up): 100.7kΩ, 49.5kΩ or 19.0kΩ yields pin voltages of 1.7V, 1.1V or 0.5V, consistent with a non-present pull resistor in the DSP. With a pull-up in the DSP, these would have been expected as 2.5V, 2.0V and 1.2V (minimums) respectively.

    The "input current" is specified in Section 5.5 on pg. 79 of sprs590f as 70uA - 310uA. The terminology is obviously a bit inaccurate. Those currents will not flow in all circumstances. What is actually implied is the "maximum input current", i.e. if you were to ground a pin featuring an internal pull-up (like nReset), at least 70uA should flow out of the pin. I measure about 0.4uA out of the pin in this case (with VIO = 3.32V).

    Even if I change the external pull-up to 4.7kΩ, I cannot measure more than about 0.4uA out of the pin.

    What currents are you able to draw from the nReset pin? Can you post your measurements, specifying your supply voltage, please?

    Thanks,
    Bernhard

  • Hello TI, any response to this enquiry, please?

  • Benhard,

    I am working on this query. I will update you soon.

    Regards,
    Senthil
  • Bernhard,

    As far as i know, the input current specifications are provided based on the characterization that we performed during the initial period. Unfortunately i do not have any of its data to share with you.

    What is the voltage you are seeing at nRESET pin without any external resistor ?

    Are you seeing the same behavior on any other pin having internal pull-up resistor ?

    I will also check with the design team if i can get any information to share with you.

    Regards,
    Senthil

  • Hello TI USA / Design Team,

    Is someone perhaps able to assist me with recent practical measurements on the latest Silicon 2.3 to confirm that a pull-up is indeed implemented on the nReset pin of the C6748 processor?

    The assertion is that this feature is out of spec and should be documented in an updated datasheet or in updated Errata.

    Regards,

    Bernhard

  • Hi Bernhard
    I am investigating this further.
    As per my review of the chip specifications on this pin does not call out that it has an internal pull up, but I am surprised that this has not come up prior, so let me dig through this further.
    It is an old device, so this may take some time.

    Few things that I do want to point out
    1) There has been no change in design between PG2.3 vs older for this pin or this aspect of the design.
    2) There is a section in the datasheet that recommends that for key configuration pins and boot pins, it is strongly recommended not to rely on internal pu/pd, reset is definitely one such pin, so my recommendation is that you do not rely on the IPU etc, irrespective of this discussion
    3) There are no plans to put any additional char data or specification updates in the datasheet for these devices.

    e2e.ti.com/.../841448

    I will hopefully get a clarification soon on the IPU and if it is not present , we will take the corrective action to fix it in the upcoming rev of the datasheet.

    Regards
    Mukul
  • Hi Bernhard
    I managed to pull out the design files for this and indeed on the RESET line there is no IPU.
    This seems to be a typo in the datasheet from 2011 time frame.
    I have submitted a litbug to get this fixed.
    I regret the time you have had to put to experiment with this.

    Regards
    Mukul
  • Hello Mukul,

    A. Thank you very much for making the effort to check this on your side and to give this confirmation. Pity that it takes a week in this forum to get more than superficial attention, but thank you very much for taking the trouble and actually doing so.

    1. Please also confirm the new input current specs of the nReset pin.

    B. Unfortunately, it seems as if there are more problems with the pull resistors, including the CP[xx] (configurable pull) resistors and their default pull state. I am investigating this but perhaps you can save us a lot of time by comparing the design files you have access to to

    1. the pins as listed in column "PULL" in Table 3-5 of the sprs590f datasheet

    2. the default pull directions for the CP[xx] pins as listed in Table 10-54 of spruh79a (TMS320C6748 DSP Technical Reference Manual)

    In fact, initial investigations show differences even within a CP[xx] group, so please could you also check

    3. the CP[xx] group assignments listed in column "PULL" in Table 3-5 of the sprs590f datasheet to see if these are correct

    Look forward to hearing from you on the 4 points raised above.

    Thanks,

    Bernhard

  • Hello Mukul,

    An update on my allegations on the CP[xx] pull resistors and their states after reset:

    I have carefully measured about 80 pins with fixed and CP[xx] resistors, and all of the ones I measured so far were implemented correctly according to the documentation cited in my previous post, so only the nReset pin seems to be out of spec at this stage.

    Thank you very much once again for your help - if you could just confirm the new input current specs on the nReset pin, this would be great.

    Bernhard
  • Hi Bernhard
    Thanks for the update, I should've mentioned that when I posted my responses, I had done another sanity check to ensure other pin values are correct. Too bad that you took these measurements, but hopefully that adds some confidence on our documentation.
    I am still surprised that this has not come up in in 5+ yrs.

    On the input current spec, I double checked the archives and it is 9uA , as listed for VSS with opposing internal resistor spec
    Let me know if you see any confusion.

    Regards
    Mukul
  • Thanks Mukul. Could you perhaps also confirm that this current will always flow OUT of the pin, ie. that a tiny pull-UP is effectively still implemented in the DSP, though weak? Or is there a chance that current could flow INTO the pin, looking like an IPD under some circumstances?

  • Hi Bernhard
    Sorry I missed this query. Actually there is no way to tell, it can be either depending on the logic levels hooked up to the IO etc.
    Hope this helps.
    Regards
    Mukul
  • Hello Mukul, when is updated documentation reflecting this bug expected?

  • Hi Bernhard.

    Let me check with the documentation team. Usually we try to accrue several literature bugs before we spin a new version of the datasheet, unless we have a really critical bug etc.

    I will see what is the schedule for refresh and outstanding literature bugs, and get back to you.

    Regards

    Mukul