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Juggling two slave McASP

Sergey Kolchanov
Prodigy 250 points

Hi all!

I am working on an application which is supposed to read audio data from two sources and write to one destination in real time. Both sources need to be I2S masters by technical restrictions. Thats why I have used McASP1 to deal with one of the sources (input and output) and McASP0 to deal with another one on DSP side (c6747). Also I have tuned EDMA with double-buffering. Now the system sounds almost good, but not perfect. The problem is that two clock crystalls are different and independent. BCLK differs only for 0.1 KHz (3.072 vs 3.0721) but anyway sometimes there is two EDMA events from McASP0 versus only one event from McASP1.

Is there any possible solution? Preferrebly without changing hardware architecture:)

Thank you.

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    Why don't you try McASP0 and McASP1 to receive audio samples at different sample rate since there is clocking flexibility which would allow the McASP's to receive and transmit at different rates and by this, McASP can receive data at 48Ksps but while transmit data, it has the flexibility to up-sample at 96Ksps or 192Ksps.

    But in general, it would be better to operate both transmit and receive sections of McASP synchronously at same sample rate. Please refer Section 24.1.2 in the C6747 TRM as below:

    http://www.ti.com/lit/ug/spruh91b/spruh91b.pdf

    You can also refer the below E2E thread to get an idea of changing sample rates:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/214513/766354.aspx#766354

    Also, you could also check to detect any CLKERR  at the i2S interface thru. XSTAT & RSTAT. One thing, you can do is to probe the CLK, FS & corresponding AXR[n] pins thru. an oscilloscope since I2S format is specifically designed to transfer a stereo channel (left and right) over a single data pin AXR[n].

    Note: To transmit in I2S format, use MSB first, left aligned, and also select XDATDLY = 01,  RDATDLY = 01 ((1 bit delay) (Refer Table 24-4 & Table 24-5 from the above C6747 TRM doc.)

    May be you can check this E2E post to validate McASP initialization with I2S format:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/283841.aspx

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 250 points
    Good answer, bad news for me.