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C6727 EMIF GPIO lines

Junie Madrid
Prodigy 140 points

Hi,


I can't find details about how the chosen GPIO lines for higher addresses are used by EMIF on c6727.  I've read both SPRS370E (c6727 data sheet) and SPRU711C (EMIF user's guide) but the only mention about this is that "Any GPIO-capable pins which can be pulled down at reset can be used to control ..." higher address pins.

So how would I know which of the chosen GPIO pins correspond to, for example A[16] or to A[18] pin of the external NVRAM?  Does the EMIF controller decide based on the order of the GPIO pins? So if I choose a block of 6 UHPI pins as GPIO for A[13]-A[18] lines of NVRAM, which corresponds to which among those pins?

I can't find it anywhere detailed.  I'd appreciate any help.  Thank you.

  • 0
    TI__Mastermind 43660 points
    Junie,

    You may need to use bootloader which would configure the GPIO as address lines.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 140 points
    Senthil,

    I get the GPIO setting in software. Just enable GPIO on pins you want, but when it leaves the lines physically, how does it look? I want to use say UHPI_HA[5:0] as GPIO. I'm talking connections. How do I make sure that UHPI_HA[5] == A[18], UHPI_HA[4] == A[17] on NVRAM, and so on. How do I find that out? Where is that mentioned or configured?

    Thanks.
  • 0
    TI__Guru** 114410 points
    The GPIO based expandable address space is completely software controlled and not some thing that the EMIF controller will manage.
    Typically, you would create a software layer for memory fetches that will decode the memory address into GPIO bit-bang configurations on the higher address lines and let EMIF handle the lower address lines.
  • 0 in reply to Rahul Prabhu
    Prodigy 140 points

    Thank you for your response.  But this is what I really, really need to understand.

    From what I know, for 8-bit Async interface, this is how the EM_A lines correspond to the external memory:

    EMIF              External NVRAM

    ---------------   ------------------------

    EM_A[12]  ->  A[14]

    EM_A[11]  ->  A[13]

    ...

    EM_A[0]   ->  A[2]

    EM_BA[1] ->  A[1]

    EM_BA[0] ->  A[0]

    Correct so far?

    Now my NVRAM HAS 6 MORE address pins (A[15] to A[20]).  My question is What do I *physically* connect to these pins (think schematics, I have those 6 address pins that should be connected to something)?

    I will enable UHPI pins as GPIO[5:0].  So do I physically connect UHPI_HA[0] to A[15], UHPI_HA[1] to A[16], and so on?  Is this (always) the case?

    How does the EMIF controller decide to choose which among the 6 GPIO pins correspond to which of the 6 A[x] pins?

    Please help me understand in the simplest, most detailed you can explain.  If I'm understanding this incorrectly, please let me know.  Thank you very much for your help.

  • 0 in reply to Junie Madrid
    TI__Mastermind 43660 points
    Junie,

    Yes, your understanding is correct. You can connect UHPI_HA[0] to A[15], UHPI_HA[1] to A[16], and so on. You may need to define which GPIO corresponds to the which address line in the software. As Rahul mentioned, you would create a software layer to manage and decode the memory address.

    Please refer below similar thread which explains about using GPIO for EMIF addressing.

    e2e.ti.com/.../110467

    Regards,
    Senthil