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Problem while setting up AMUTEIN0 to generate INT13 on TMS320C6727B (Interrupt routine is not executing)

Hi,

I am unable to execute ISR hooked up to INT13 of C6727. I configured an external pin(SPI0_ENA) as source of AMUTEIN0 and configured dMAX to generate event26 and INT13. My code is given below. Plz suggest me, where is the problem. I get bit 26 of DEFR flag register '1' when interrupt occurs on SPI0 ENA pin but interrupt routine is not executed at all.

///////////////////////////////////////////////////////Code//////////////////////////////////////////////////////////////////////////

void main (void)

{
//dMAX settings to use AMUTEIN0 for generation of event 26 on dMAX
*(unsigned int*)(0x60000008)= 0x04000000; // DEPR[26]=1 event polarity set to rising edge
*(unsigned int*)(0x60000014)= 0x04000000; // DEHPR[26]=1 event high priority set
*(unsigned int*)(0x6000000C)= 0x04000000; // DEER[26]=0 enable event 26(associated with AMUTEIN0),(CPU INT13)

//Selection of input pin for AMUTEIN0

*(unsigned int*)(0x40000018)= 0x00000007; // setting reg CFGMCASP0 to source AMUTEIN0 from SPI0_ENA/I2C_SDA 
*(unsigned int*)(0x44000048)= 0x00000000; // AMUTE register

//Settings for SPI0_ENA/I2C_SDA pin
*(unsigned int*)(0x47000014)= 0x00000000; // SPIPCO[8]=0 to set SPI0_ENA as GPIO
*(unsigned int*)(0x47000018)= 0x00000000; // SPIPC1[8]=0 to set SPI0_ENA as input

*(unsigned int*)(0x61008068)= 0x00000607; // event entry for INT13

/* relocating the Interrupt Vector Table */

CSL_intcSetVectorPtr(0x10000000);

/* variables for installing handler for Rti interrupts */
CSL_IntcObj intcObj;

CSL_IntcEventEnableState state;

CSL_IntcEventHandlerRecord isrRec;

CSL_Status status = CSL_SOK;

/* interrupt variables decalation */
CSL_IntcDispatcherContext intcDispatcherContext;

CSL_IntcContext intcContext;


memset (&intcContext, 0, sizeof(CSL_IntcContext));
memset (&intcDispatcherContext, 0, sizeof(CSL_IntcDispatcherContext));


/* Interrupt Initialization */
status = CSL_intcInit(&intcContext);
if (status != CSL_SOK) {
printf ("INTC: init....failed\n");
intcTestFail++;
return;
}

/* disabling Global Interrupt */

status = CSL_intcGlobalDisable(&state);
if (status != CSL_SOK) {
printf ("INTC: intc Global Disable....failed\n");
intcTestFail++;
return;
}

/* Directly adding the isr address to the fetch packet */

status = CSL_intcHookIsr(13, (Uint32)comp1Isr);
if (status != CSL_SOK) {
printf ("INTC: intc Hooking of isr....failed\n");
intcTestFail++;
intc_error_exit ();
return;
}

/* Enabling interrupt 13 */
status = CSL_intcEventEnable(13, &state);
if (status != CSL_SOK) {
printf ("INTC: intc nmi event enable....failed\n");
intcTestFail++;
intc_error_exit ();
return;
}

/* Enabling non-maskable interrupt */
status = CSL_intcEventEnable(1, &state);
if (status != CSL_SOK) {
printf ("INTC: intc nmi event enable....failed\n");
intcTestFail++;
intc_error_exit ();
return;
}

status = CSL_intcGlobalEnable(&state);

if (status != CSL_SOK) {
printf ("INTC: intc global enable....failed\n");
intcTestFail++;
intc_error_exit ();
return;
}

status = CSL_intcClose (hIntc);

while(1);
}

/////////////////////////////////////////////////////////////////////////////////////////////
interrupt void comp1Isr ()
{
printf ("\n INT13 \n");
}

void intc_error_exit (void)
{
CSL_intcClose (hIntc);
}

  • Hi,

    Thanks for your post.

    Basically, the C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in combination with a McASP AMUTEIN signal to provide external interrupt capability.  I think, there are few points needs to be considered when using the AMUTEIN signal to enable external interrupts which are below:

    1. The I/O pin selected by the CFGMCASP0/1/2 registers should be configured as a general-purpose input pin within the associated peripheral. Also, the AMUTEIN signal should be disabled within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active.

    2. AMUTEIN events are logically OR-ed with the McASP transmit and receive error events within the dMAX, therefore, the ISR that processes the dMAX interrupt generated by these events must recognize the source of the event. For more details, please refer Section 4.10 in the C6727 datasheet below:

    http://www.ti.com/lit/ds/symlink/tms320c6727.pdf

    I think, you can check the below E2E thread with dMAX servicing the SPI data transfer requests to trigger CPU and to synchronize dMAX with SPI events:

    https://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/12203#pi317286=1

    As well you could refer Appendix B for programming SPI and example codes for dMAX servicing the SPI data request, kindly refer B.1.1 & B.1.2 from SPI reference guide as below:

    http://www.ti.com.cn/cn/lit/ug/spru718b/spru718b.pdf

    Thanks & regards,

    Sivaraj K

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