How to setup an EDMA transfer from L2RAM to external address on C6713

Jens Biltoft

I am trying to make my C6713 DSP transfer a small block of data from its internal RAM to an FPGA that is connected via the External memory interface using an EDMA transfer.

I have previously used a QDMA transfer to copy the data from DSP to a FIFO in the same FPGA, but now I would like to remove the FIFO implementation and copy the data to a RAM block in the FPGA instead.

The QDMA used to be configured in the following way

EDMA_Config RIHighSpeedOutQDMA = {
    0x2900000,      /*  Option  DUM = NONE */
    (Uint32) &stHighSpeedRiDspOut,                                              /*  Source Address - Data structure in L2RAM  */
    0x00000000,        /*  Transfer Counter - Numeric  This is setup later*/
    (Uint32) FPGA_RIDSP_HS_DATA_OUT_FIFO_ADDR,        /*  Destination Address - FIFO in FPGA addr = 0xB0000100*/
    0x00000000,        /*  Index register - Numeric  */
    0x00000000         /*  Element Count Reload and Link Address  */
};

void cslCfgInit()/* called from main*/
{
    RIHighSpeedOutQDMA.cnt = EDMA_CNT_RMK(0,sizeof(stHighSpeedRiDspOut)/sizeof(uint16));  /* Set the number of words to transfer */
}

myPeriodicFunction()
{
    EDMA_qdmaConfig(&GIHighSpeedOutQDMA);
}

As you can see the options for the EDMA configurations indicates that it is a 1D to 1D transfer with SUM = INC and DUM = NONE

So I thought it should be enough to change the options for the EDMA configurations to SUM = INC and DUM = INC

so I changed it to

EDMA_Config RIHighSpeedOutQDMA = {
    0x2920000,        /*  Option  DUM = INC  */
    (Uint32) &stHighSpeedRiDspOut,        /*  Source Address - same as before  */
    0x00000000,        /*  Transfer Counter - Numeric  */
    (Uint32) FPGA_RIDSP_HS_DATA_OUT_ADDR,        /*  Destination Address - in FPGA addr = 0xB0000100 */
    0x00000000,        /*  Index register - Numeric  */
    0x00000000         /*  Element Count Reload and Link Address  */
};

Other than that it is only the address in the FPGA that have changed everything regarding the QDMA is the same. But Now I no longer gets any data transfered - none what so ever.

I have verified that if I use the CPU to copy the data from DSP to FPGA then it works as expected, so I know that I am able to write the data to the FPGA.

I use

DSPBIOS 5_41_11_38

C6xCSL

compiler 7.4.12

I have tried alot of different things including a normal EDMA instead of QDMA, but I just cant get any data from DSP to FPGA

Are there any restrictions when using DMA to copy data from L2RAM to External RAM?

Best

Jens

FPGA addr = 0xB0000100Best
Jens

over 7 years ago

0 RandyP over 7 years ago

TI__Guru* 84110 points

Jens,

You have not mapped the binary field values correctly from your intended values to the hex values shown. Please check the bit field positions for the DUM field. I find it helpful to always maintain 8 hex chars to avoid a mis-count of 4-bit nibble positions.

This should not affect the fact of the transfers, however. You should see at least one value transferred and you should see activity on the EMIF bus during this transfer.

For a test, change the destination address to a spare location in RAM. This could be internal or external. Initialize the destination area with some values and then do the transfer, observing the results in RAM.

Regards,
RandyP

0 Jens Biltoft over 7 years ago in reply to RandyP

Expert 1220 points

Hi Randy

Thanks for the suggestion, it could have been helpfull if you could come with a suggestion to what the correct value for the option field should be.

I have rechecked the values that I have, but as far as I can see the value is correct so I am still stuck. You can see the table I use for finding the hex value here.

Bit   |31 29|28 27| 26|25 24| 23|22 21| 20  |19 16|15           2  | 1  | 0 |   
Field |PRI  |ESIZE|2DS| SUM |2DD| DUM |TCINT| TCC |Reserved        |LINK| FS|
value |  1  |   1 | 0 |   1 | 0 |  1  |  0  |  0  |    0           | 0  | 0 |
bin   |001  |  01 | 0 |  01 | 0 | 01  |  0  |0000 |00000000000000  | 0  | 0 |

4-bin |  0010   |  1001     |     0010      |0000 |0000|0000|0000|0000      |
Hex   |   2     |    9      |       2       |  0  | 0  |  0 |  0 |  0       |

I will try to make a RAM to RAM copy to verify the setup

Jens

0 RandyP over 7 years ago in reply to Jens Biltoft

TI__Guru* 84110 points

Jens,

Excellent formatting to get the columns to line up. That is hard to do. Did you have to change the font in the rich editor or did it work that way automatically when you use the Insert Code feature?

Your hex value above does not match the hex value in your code. In your code you only have 7 hex digits instead of 8. Fixing that might solve your problem. Since it was working before, you either lucked out with bit positions or made a minor omission when you tried to write the new code.

Please keep us posted on this. And I would comment that if this is a new design, you might consider the C6748 which is a newer and more powerful floating-point DSP. And more people at TI will have experience on it to help you.

Regards,
RandyP

0 Jens Biltoft over 7 years ago in reply to RandyP

Expert 1220 points

Oh my God that is embarrassing!

I have been looking at that number and double checking it for a week now, without seeing that I missed a 0.

I am so glad you could see it.

When I changed to the options from 0x2920000 to 0x29200000 everything startetd to work :-)

Actually I changed to setup to use some of the EDMA_OPT_RMK() macro from the CSL so now it looks like this

EDMA_Config RIHighSpeedOutQDMA = {
    EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_INC,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_INC,
        EDMA_OPT_TCINT_NO,
        0,
        EDMA_OPT_LINK_NO,
        EDMA_OPT_FS_NO),
    (Uint32) &stHighSpeedRiDspOut,        /*  Source Address - From User's Header File  */
    0x00000000,        /*  Transfer Counter - Numeric  */
    (Uint32) FPGA_RIDSP_HS_DATA_OUT_ADDR,        /*  Destination Address - From User's Header file  */
    0x00000000,        /*  Index register - Numeric  */
    0x00000000         /*  Element Count Reload and Link Address  */
};

To answer your question,

First to get the columns lined up i wrote the text in a text editor, and pasted it into the the Insert Code feature so that was not so hard.

Second the design is not new at all, I guess it is about 15 years old. We already did a redesign of our controller board where we switched to the Keystone 1 processor which has given us a much more powerfull platform. This change to the code is just to add some stability to our older products.

Thanks again

Jens

embarrassing

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How to setup an EDMA transfer from L2RAM to external address on C6713