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TMS320C6701: Asynchronous Memory Cycle Timing Diagramm for DMA from an Dual Port Memory

Part Number: TMS320C6701

Hi Team,

my customer is looking for an Asynchronous Memory Cycle Timing Diagramm for DMA (Burst) reads or writes from an Dual Port Memory with ARDY Output.
 They use an asynchronous SRAM Interface with ARDY Input to C6701 and burst transfers.

Could you provide a combined timing diagrams for async Access with ARDT and DMA/Burst?

Thank you in advance and kind regards,

Sally