TMS320C6455: regarding multiple events

Hi,

Are you using the Processor SDK source code or is this a bare metal example or some other software?

Best Regards,
Yordan

HI,

I am using CSL calls for enabling the events and for hooking my isr

Surabhi,

There is not enough information here to guess what you are doing in your code, either right or wrong.

SURABHI RAKESH said:

When we are enabling  multiple interrupts , only the latest enabled interrupt is working and it is overwriting the first interrupt.

This is not clear. When you enable an interrupt, how does that overwrite another interrupt? Do you mean the first ISR is overwritten when the second interrupt is enabled?

Or do you mean the first interrupt is no longer enabled? If that is the case, then the command you use may be writing a full value to the enable register instead of doing a read-modify-write.

There are a lot of registers in the interrupt paths, so please be specific about the registers and commands you are using.

SURABHI RAKESH said:

But when I see my event set register (the corresponding events are set) and even the INTMUX register is showing the event that is hooked with this VectId.

What event set register are you talking about?

My recollection is that INTMUX merely shows what the interrupt mapping is. Is does not indicate any status.

If you are developing a new project on this board, you must start from one of our working examples, preferably on an EVM/DSK first so you will know the difference between hardware and software issues. Why are you starting a new project with an old device like this? Or is this an old board, in which case you should have some of your own internal working examples.

The C6455 is a very capable and powerful fixed-point DSP. But it is very complex in its internal features, including the interrupts. This is why you must start from a working example, and then carefully read through the documentation to understand how it works.

Regards,
RandyP

HI Randy,

In my application, I have configured two GPIOas interrupts (GPIO3 and GPIO5) both not occuring at the same instance .Later using seperate CSL calls i have configured vectid12 for event 54(GPIO3 event) and vectid 9 for event 56(GPIO5 event) and hooked the corresponding isr's (where in isr I am updating two seperate memory loctaion that holds no of times corresponding interrupt has detected by cpu).

We have observed that
1. When the configuration file as placed as below
gpio5_interrupt();
gpio3_interrupt();
Only GPIO3 interrupt is received by DSP

2.. When the configuration file as placed as below
gpio3_interrupt();
gpio5_interrupt();
Only GPIO5 interrupt is received by DSP

As per document provided by TI(spru871k)(section 7.5.1.1) says EFR shows the event that has occured.In my application EFR shows that both the events have occured

But my instructions placed in isr is not working(by looking the memory location)

Regards
Rakesh

Rakesh,

vaishnavi gujjula said:

We have observed that
1. When the configuration file as placed as below
gpio5_interrupt();
gpio3_interrupt();
Only GPIO3 interrupt is received by DSP

It is clear that your team's skill is good at writing code and using the DSP. We will need terminology to be as precise as possible in order to exchange the technical details that are causing your problem.

"configuration file" usually refers to a file with extension .cfg or something similar and that file is used by the O/S at compile time to configure parts of your program. Are you using an O/S such as DSP/BIOS or SYS/BIOS or TI-RTOS for this application?

For now, I will assume that what you call "configuration file" is your set of C functions in a C source file such as main.c, and that you are using this sequence of commands to configure the interrupts (and other things). If this is the case, where did the functions gpio3_interrupt() and gpio5_interrupt() come from? I do not recognize these as TI CSL commands. If these are functions you wrote, then it would seem logical that they are written incorrectly based on your observations. Do you agree with my interpretation?

vaishnavi gujjula said:

As per document provided by TI(spru871k)(section 7.5.1.1) says EFR shows the event that has occured.In my application EFR shows that both the events have occured

In my copy of SPRU871, section 7.5.1.1 describes the EVTFLAGn registers. EFR is the Exception Flag Register and is described elsewhere. EFR should not be a part of the interrupt configuration. The EVTFLAGn registers can be useful to see that the interrupt events have occurred, but they are not directly involved in the interrupt path you are trying to get working. EVTFLAGn are only used when the Event Combiner is used to generate EVT[3:0]; you are using direct mapping of your two GPIOn interrupts to DSP INT15-4.

Please locate a CSL example project or source file that will show you how to setup the interrupts. It is much easier to start from a working example and then modify it to implement the exact features you need, than it is to write your own code and try to debug it - especially debugging it remotely.

Regards,
RandyP

Hi Randy,
Yes,the meaning of configuration is a set of C code that will configure GPIO as interrupt .the same is attached below

With the below code we are facing those issues,
Could you please send the link of CSL examples for multiple interrupts.

The same problems above is faced even after clearing our corresponding events in ISR.
We were speaking of EventFlag register only.

void gpio3_interrupt(void)
{
CSL_Status intStat_sp;
CSL_GpioPinConfig config_sp;
CSL_Status status_sp;
CSL_GpioContext pContext_sp;
CSL_GpioObj gpioObj_sp;
CSL_GpioHwSetup hwSetup_sp;
CSL_IntcGlobalEnableState state_sp;
CSL_IntcParam vectId_sp;


/* Initialize INTC */
context_sp.numEvtEntries = 1;
context_sp.eventhandlerRecord = record_sp;

intStat_sp = CSL_intcInit(&context_sp);
if (intStat_sp != CSL_SOK) {
printf("INTR: Initialization error.\n");
demoFail++;
return;
}

/* Enable NMIs */
intStat_sp = CSL_intcGlobalNmiEnable();
if (intStat_sp != CSL_SOK) {
printf("INTR: Error while enabling NMI.\n");
demoFail++;
return;
}

/* Enable all interrupts */
intStat_sp = CSL_intcGlobalEnable(&state_sp);
if (intStat_sp != CSL_SOK) {
printf("INTR: Error while enabling interrupt.\n");
demoFail++;
return;
}

/* Open interrupt module */
vectId_sp = CSL_INTC_VECTID_12;

gpioIntcHandle_sp = CSL_intcOpen(&gpioIntcObj_sp, CSL_INTC_EVENTID_GPINT3,
&vectId_sp, &intStat_sp);
if ((gpioIntcHandle_sp == NULL) || (intStat_sp != CSL_SOK)) {
printf("INTR: Error opening the instance.\n");
demoFail++;
return;
}

/* Bind ISR to Interrupt */
isr_gpio_sp.handler = (CSL_IntcEventHandler)&ISR_GPIO3;
isr_gpio_sp.arg = gpioIntcHandle_sp;
CSL_intcPlugEventHandler(gpioIntcHandle_sp, &isr_gpio_sp);

/* Event Enable */
CSL_intcHwControl(gpioIntcHandle_sp, CSL_INTC_CMD_EVTENABLE, NULL);
if (intStat_sp != CSL_SOK) {
printf("INTR: Error in enabling event.\n");
demoFail++;
return;
}

/* Initialize the GPIO CSL module */
status_sp = CSL_gpioInit(&pContext_sp);
if (status_sp != CSL_SOK) {
printf("GPIO: Initialization error.\n");
demoFail++;
return;
}

/* Open the CSL module */
hGpio_sp = CSL_gpioOpen(&gpioObj_sp, CSL_GPIO, NULL, &status_sp);
if ((hGpio_sp == NULL) || (status_sp != CSL_SOK)) {
printf("GPIO: Error opening the instance.\n");
demoFail++;
return;
}

/* Setup hardware parameters */
hwSetup_sp.extendSetup = NULL;

/* Setup the General Purpose IO */
status_sp = CSL_gpioHwSetup(hGpio_sp, &hwSetup_sp);


/* Configure pin 3 to rcv an interrupt on Rising Edge
*/
config_sp.pinNum = CSL_GPIO_PIN3;
config_sp.trigger = CSL_GPIO_TRIG_RISING_EDGE;
config_sp.direction = CSL_GPIO_DIR_INPUT;

/* Enable the bank interrupt */
status_sp = CSL_gpioHwControl(hGpio_sp, CSL_GPIO_CMD_BANK_INT_ENABLE, NULL);
if (status_sp != CSL_SOK) {
printf("GPIO: Command to enable bank interrupt... Failed.\n");
demoFail++;
}

/* configure the gpio pin 3 */
status_sp = CSL_gpioHwControl(hGpio_sp, CSL_GPIO_CMD_CONFIG_BIT, &config_sp);
if (status_sp != CSL_SOK) {
printf("GPIO: GPIO pin configuration error.\n");(EVTFLAG2)
demoFail++;
return;
}
}


void gpio5_interrupt(void)
{
CSL_Status intStat_sp_rc;
CSL_GpioPinConfig config_sp_rc;
CSL_Status status_sp_rc;
CSL_GpioContext pContext_sp_rc;
CSL_GpioObj gpioObj_sp_rc;
CSL_GpioHwSetup hwSetup_sp_rc;
CSL_IntcGlobalEnableState state_sp_rc;
CSL_IntcParam vectId_sp_rc;


/* Initialize INTC */
context_sp_rc.numEvtEntries = 1;
context_sp_rc.eventhandlerRecord = record;

intStat_sp_rc = CSL_intcInit(&context_sp_rc);
if (intStat_sp_rc != CSL_SOK) {
printf("INTR: Initialization error.\n");
demoFail++;
return;(EVTFLAG2)
}

/* Enable NMIs */
intStat_sp_rc = CSL_intcGlobalNmiEnable();
if (intStat_sp_rc != CSL_SOK) {
printf("INTR: Error while enabling NMI.\n");
demoFail++;
return;
}

/* Enable all interrupts */
intStat_sp_rc = CSL_intcGlobalEnable(&state_sp_rc);
if (intStat_sp_rc != CSL_SOK) {
printf("INTR: Error while enabling interrupt.\n");(EVTFLAG2)
demoFail++;
return;
}

/* Open interrupt module */
vectId_sp_rc = CSL_INTC_VECTID_9;

gpioIntcHandle_sp_rc = CSL_intcOpen(&gpioIntcObj_sp_rc, CSL_INTC_EVENTID_GPINT5,
&vectId_sp_rc, &intStat_sp_rc);
if ((gpioIntcHandle_sp_rc == NULL) || (intStat_sp_rc != CSL_SOK)) {
printf("INTR: Error opening the instance.\n");
demoFail++;
return;(EVTFLAG2)
}

/* Bind ISR to Interrupt */
isr_gpio_sp_rc.handler = (CSL_IntcEventHandler)&ISR_GPIO5;
isr_gpio_sp_rc.arg = gpioIntcHandle_sp_rc;
CSL_intcPlugEventHandler(gpioIntcHandle_sp_rc, &isr_gpio_sp_rc);

/* Event Enable */
CSL_intcHwControl(gpioIntcHandle_sp_rc, CSL_INTC_CMD_EVTENABLE, NULL);
if (intStat_sp_rc != CSL_SOK) {
printf("INTR: Error in enabling event.\n");
demoFail++;
return;
}

/* Initialize the GPIO CSL module */(EVTFLAG2)
status_sp_rc = CSL_gpioInit(&pContext_sp_rc);
if (status_sp_rc != CSL_SOK) {
printf("GPIO: Initialization error.\n");
demoFail++;
return;
}

/* Open the CSL module */
hGpio_sp_rc = CSL_gpioOpen(&gpioObj_sp_rc, CSL_GPIO, NULL, &status_sp_rc);
if ((hGpio_sp_rc == NULL) || (status_sp_rc != CSL_SOK)) {
printf("GPIO: Error opening the instance.\n");
demoFail++;
return;(EVTFLAG2)
}

/* Setup hardware parameters */
hwSetup_sp_rc.extendSetup = NULL;

/* Setup the General Purpose IO */
status_sp_rc = CSL_gpioHwSetup(hGpio_sp_rc, &hwSetup_sp_rc);


/* Configure pin 5 to generate an interrupt on Risp_booted=1;sing Edge, and
* configure it as an output, then set the data High (Low->High).
* Set Trigger:
*/
config_sp_rc.pinNum = CSL_GPIO_PIN5;
config_sp_rc.trigger = CSL_GPIO_TRIG_RISING_EDGE;
config_sp_rc.direction = CSL_GPIO_DIR_INPUT;

/* Enable the bank interrupt */
status_sp_rc = CSL_gpioHwControl(hGpio_sp_rc, CSL_GPIO_CMD_BANK_INT_ENABLE, NULL);
if (status_sp_rc != CSL_SOK) {(EVTFLAG2)
printf("GPIO: Command to enable bank interrupt... Failed.\n");
demoFail++;
}

/* configure the gpio pin5 */
status_sp_rc = CSL_gpioHwControl(hGpio_sp_rc, CSL_GPIO_CMD_CONFIG_BIT, &config_sp_rc);
if (status_sp_rc != CSL_SOK) {
printf("GPIO: GPIO pin configuration error.\n");
demoFail++;
return;
}
}




void ISR_GPIO5 (void *arg)
{
a++;
}

void ISR_GPIO3 (void *arg)
{
b++;
}


Regards,
Rakesh