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Part Number: TMDSLCDK6748
From the schematics document provided by TI, the SPI0_CSn pins are connected to the LAN chip, U23. They are not available in the output headers. I require a 4 wire SPI communication for my application. Is it possible to use the SPI0 communication in 3 wire mode (ie, SIMO, SOMI, SCLK) and providing the CSn using the GPIO pins available ? What are the other possible solutions ?
with regardsHarikrishnan R S
.Thank you .
The pins SPI0_sCSn_4 and SPI0_sCSn_5 are multiplexed with the UART_TXD and UART_RXD respectively. After populating the R218 and R219 resistors, will it be possible to use the 29th and 31st pins of J15 pin header as SPI0_sCSn_4 and SPI0_sCSn_5 ?
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In reply to Harikrishnan R S:
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