Hello TI - experts,
could you please assist me in the following topic, in fact an issue.
Application description |
DSP-application running on C6414 (TMS320C6414TCLZ of last silicon revision 2.0) makes use of all three McBSP ports driving EDMA. McBSPs running in TDM mode (128 timeslots each), get clocked completely externally. Clock for all three McBSPs is of the same origin: FPGA spreads the same serial bitclock and frameclock as external clocks to all three McBSPs. Shared EDMA_INT interrupt is used for all transfer-complete (tcc) interrupts. Out of it, EDMA CIPR (Interrupt pending register) is monitored in order to detect the transfer completion. More precisely, for certain time (XINT) interrupt waits for the TX and RX indication of completion of all 3 (McBSPs) transfer complete codes. As proposed in SPRU234C EDMA Ref-Guide (paragraph 1.15.1) the ISR checks (waits) for all pending interrupts and continues until all the posted interrupts are serviced. Speaking of (E)DMA, besides McBSP, in an application there’s only one more peripheral also utilizing EDMA: |
Initial EDMA-setup | Transfer Request Queues Q1 (3 x McBSP) and Q2 (HPI) are used (PQAR and TRCTL registers using default setup). Element synchronized 1-dimensional transfers are used. QDMA is not used. |
Issue Description |
On some boards, it happens randomly (6-10 times/24 hours) that completion of all 6 McBSP transfers (Rx & Tx for all 3 ports) takes longer time than usually! On affected boards, both RX & TX transfers for all three McBSPs get sometimes very delayed (RX transfers the most). |
Measurements performed | Of course we have performed measurements of serial clocks. At the moment of issue-occurence and some time before, no clock miss-behaviour could be observed. |
Attempts made to handle the issue |
Since requests on a single priority level are serviced serially and in order; whereas, requests on different priority levels can be serviced concurrently, I tried to change the usage of EDMA queues in order to benefit from parallelism. I changed the initial EDMA-setup by utilizing more queues for McBSPs in the following way: Unfortunately, in spite of these changes, the failure still occurs. |
My Question:
What else could I do in order to narrow down the failure? What could cause the issue?
Thanks!
Mladen