CCS/TMDSLCDK138: How fast can I go?

Hi,

I've notified the sw team. They will post their feedback directly here.

Could you please share which RTOS SDK version are you using?

Best Regards,
Yordan

my /ti/ directory has:

bios_6_52_00_12/
ccsv7/
cg_xml/
'Code Composer Studio 7.4.0.lnk'*
dsplib_c674x_3_4_0_0/
edma3_lld_2_12_05_30C/
ipc_3_47_01_00/
mathlib_c674x_3_1_1_0/
mathlib_c674x_3_1_2_1/
mathlib_rts_c674x_3_1_2_1/
ndk_2_26_00_08/
pdk_omapl138_1_0_4/
processor_sdk_rtos_omapl138_4_03_00_05/
ti-cgt-arm_16.9.3.LTS/
ti-cgt-c6000_8.2.2/
tirex-product-tree/
uia_2_21_02_07/
xdais_7_24_00_04/
xdctools_3_32_02_25_core/
xdctools_3_50_03_33_core/
xdctools_3_50_04_43_core/
xdctools_3_50_05_12_core/
zips/

Is that helpful?

Hi Adam,

Thanks for providing that info.

The BIOS.cpuFreq parameter doesn't actually change the CPU frequency, it just tells the kernel what frequency the CPU is running at.

The CPU and DDR speed is actually set in the GEL file. This is what runs when you connect to the ARM core. You can check it's console output to see what speed the CPU and DDR are running at: 

Adam Wozniak66 said:

ARM9_0: Output: Target Connected.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: Memory Map Cleared.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: Memory Map Setup Complete.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: PSC Enable Complete.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz
ARM9_0: Output: DDR initialization is in progress....
ARM9_0: Output: PLL1 init done for DDR:150MHz
ARM9_0: Output: Using DDR2 settings
ARM9_0: Output: DDR2 init for 150 MHz is done
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: DSP Wake Complete.
ARM9_0: Output: ---------------------------------------------

The GEL script currently only supports up to 456 MHz for the core and 150MHz for DDR. You can configure the device to run at this speed by going to Scripts -> Frequency Settings in CCS. 

I'll see if I can get a HW expert to comment on increasing the DDR clock speed.

In the CCS menu I see "View / Scripting Console", but nothing else that says "Scripts".
Where can I find this?

I assume in my final product I won't have the JTAG emulator connected.
*IN*CODE* how do I control these speeds?
Is the bios call not sufficient?

I see /c/ti/ccsv7/ccs_base/emulation/boards/lcdkomapl138/gel/OMAP-L138_LCDK.gel which looks like it hooks into some menu system of some kind. It looks like I *could* hard code it in there, but I don't think that's the way this is supposed to work.

...and looking closer I see "DDR" at 150MHz and "DDR2" at 150MHz. Are these refering t the same thing, or two different things?

...and EMIFA at 25MHz... ??? How do I tune all these things to maximize performance?

So...

When I make that .cfg file change ("var BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.cpuFreq.hi = 0; BIOS.cpuFreq.lo = 456000000;"), and in my code I have only "BIOS_getCpuFreq(&hz);" it reports the right frequency.

Also, in the bigtime_LCDKOMAPL138_C67XX example, the one second clock seems to be firing at 1 second intervals based on my stopwatch.

I don't understand how your statement "The BIOS.cpuFreq parameter doesn't actually change the CPU frequency" can be correct.

That is because in that example the 64 bit Timer is used as the Clock source, not the CPU clock. I believe on OMAPL138 the Timers run at 24 MHz by default.

Sorry, I should have specified that you need to first launch your target configuration to see the Scripts window. You can then connect to the core and select "Core_456Mhz_mDDR_150MHz" under Scripts -> Frequency Settings.

In a production environment, the bootloader would be used in place of the GEL file to initialize the device and its peripherals.

See: Using the OMAP-L132/L138 Bootloader Application Report

So I found the scripts menu, and did the selection, and got...

ARM9_0: Output: Target Connected.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: Memory Map Cleared.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: Memory Map Setup Complete.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: PSC Enable Complete.
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz
ARM9_0: Output: DDR initialization is in progress....
ARM9_0: Output: PLL1 init done for DDR:150MHz
ARM9_0: Output: Using DDR2 settings
ARM9_0: Output: DDR2 init for 150 MHz is done
ARM9_0: Output: ---------------------------------------------
ARM9_0: Output: DSP Wake Complete.
ARM9_0: Output: ---------------------------------------------

[This is where I selected Scripts / Frequency Settings / Core_456MHz_mDDR_150MHz

ARM9_0: Output: PLL0 init done for Core:456MHz, EMIFA:38MHz
ARM9_0: Output: DDR initialization is in progress....
Core_456MHz_mDDR_150MHz() cannot be evaluated.
Page fault occurred reading 0x01E1A100
at (*((unsigned int *) (0x01E1A000+0x100))&=~(0x00000020)) [OMAP-L138_LCDK.gel:40]
at device_PLL1(24, 1, 0, 1, 2) [OMAP-L138_LCDK.gel:416]
at Set_DDRPLL_150MHz() [OMAP-L138_LCDK.gel:434]
at Set_DDR2_150MHz() [OMAP-L138_LCDK.gel:463]
at Core_456MHz_mDDR_150MHz()

Can you explain this error (full capture in previous replies) ???

[This is where I selected Scripts / Frequency Settings / Core_456MHz_mDDR_150MHz

ARM9_0: Output: PLL0 init done for Core:456MHz, EMIFA:38MHz
ARM9_0: Output: DDR initialization is in progress....
Core_456MHz_mDDR_150MHz() cannot be evaluated.
Page fault occurred reading 0x01E1A100
at (*((unsigned int *) (0x01E1A000+0x100))&=~(0x00000020)) [OMAP-L138_LCDK.gel:40]
at device_PLL1(24, 1, 0, 1, 2) [OMAP-L138_LCDK.gel:416]
at Set_DDRPLL_150MHz() [OMAP-L138_LCDK.gel:434]
at Set_DDR2_150MHz() [OMAP-L138_LCDK.gel:463]
at Core_456MHz_mDDR_150MHz()

Hi Adam,

That is strange. I'm able to run the script fine with the board I have here, although I'm using an XDS510.

Please see if the following thread helps resolve this.