CCS/TMDSLCDK138: Clock control

Tool/software: Code Composer Studio

TMDSLCDK138 / CCS7.4

From the DSP, I'm trying to get a 44KHz square wave out on TMP64P3_OUT12.  Here's the code I'm trying, what's wrong with it?

#define TIMER64P3 ((uint32_t *) 0x01F0D000)

#define REV 0x00 // Revision Register
#define REV_VALUE 0x4472020C

#define EMUMGT (0x04/sizeof(uint32_t)) // Emulation Management Register
#define EMUMGT_SOFT (1 << 1)
#define EMUMGT_FREE (1 << 0)

#define GPINTGPEN (0x08/sizeof(uint32_t)) // GPIO Interrupt and GPIO Enable Register
#define GPINTGPEN_GPENO12 (1 << 17)
#define GPINTGPEN_GPENI12 (1 << 16)
#define GPINTGPEN_GPINT12INVO (1 << 5)
#define GPINTGPEN_GPINT12INVI (1 << 4)
#define GPINTGPEN_GPINT12ENO (1 << 1)
#define GPINTGPEN_GPINT12ENI (1 << 0)

#define GPDATGPDIR (0x0C/sizeof(uint32_t)) // GPIO Data and GPIO Direction Register
#define GPDATGPDIR_GPDIRO12 (1 << 17)
#define GPDATGPDIR_GPDIRI12 (1 << 16)
#define GPDATGPDIR_GPDATO12 (1 << 1)
#define GPDATGPDIR_GPDATI12 (1 << 0)

#define TIM12 (0x10/sizeof(uint32_t)) // Timer Counter Register 12

#define TIM34 (0x14/sizeof(uint32_t)) // Timer Counter Register 34

#define PRD12 (0x18/sizeof(uint32_t)) // Timer Period Register 12

#define PRD34 (0x1C/sizeof(uint32_t)) // Timer Period Register 34

#define TCR (0x20/sizeof(uint32_t)) // Timer Control Register
#define TCR_ENAMODE34_DISABLED (0 << 22)
#define TCR_ENAMODE34_ONETIME (1 << 22)
#define TCR_ENAMODE34_CONTINUOUS (2 << 22)
#define TCR_ENAMODE34_RELOAD (3 << 22)
#define TCR_CAPEVTMODE12_RISING (0 << 12)
#define TCR_CAPEVTMODE12_FALLING (1 << 12)
#define TCR_CAPEVTMODE12_BOTH (2 << 12)
#define TCR_CAPEVTMODE12_RESERVED (3 << 12)
#define TCR_CAPMODE12 (1 << 11)
#define TCR_READRSTMODE12 (1 << 10)
#define TCR_TIEN12 (1 << 9)
#define TCR_CLKSRC12 (1 << 8)
#define TCR_ENAMODE12_DISABLED (0 << 6)
#define TCR_ENAMODE12_ONETIME (1 << 6)
#define TCR_ENAMODE12_CONTINUOUS (2 << 6)
#define TCR_ENAMODE12_RELOAD (3 << 6)
#define TCR_PWID12_ONE (0 << 4)
#define TCR_PWID12_TWO (1 << 4)
#define TCR_PWID12_THREE (2 << 4)
#define TCR_PWID12_FOUR (3 << 4)
#define TCR_CP12 (1 << 3)
#define TCR_INVINP12 (1 << 2)
#define TCR_INVOUTP12 (1 << 1)
#define TCR_TSTAT12 (1 << 0)

#define TGCR (0x24/sizeof(uint32_t)) // Timer Global Control Register
#define TGCR_TDDR34(x) (((x) & 0xF) << 12)
#define TGCR_PSC34(x) (((x) & 0xF) << 12)
#define TGCR_PLUSEN (1 << 4)
#define TGCR_TIMMODE_SINGLE (0 << 2)
#define TGCR_TIMMODE_DUAL_UNCHAINED (1 << 2)
#define TGCR_TIMMODE_WATCHDOG (2 << 2)
#define TGCR_TIMMODE_DUAL_CHAINED (3 << 2)
#define TGCR_TIM34RS (1 << 1)
#define TGCR_TIM12RS (1 << 0)

#define WDTCR (0x28/sizeof(uint32_t)) // Watchdog Timer Control Register
#define WDTCR_WDKEY(x) (((x) & 0xFFFF) << 16)
#define WDTCR_WDKEY_1 0xA5C6
#define WDTCR_WDKEY_2 0xDA7E
#define WDTCR_WDFLAG (1 << 15)
#define WDTCR_WDEN (1 << 14)

#define REL12 (0x34/sizeof(uint32_t)) // Timer Reload Register 12

#define REL34 (0x38/sizeof(uint32_t)) // Timer Reload Register 34

#define CAP12 (0x3C/sizeof(uint32_t)) // Timer Capture Register 12

#define CAP34 (0x40/sizeof(uint32_t)) // Timer Capture Register 34

#define INTCTLSTAT (0x44/sizeof(uint32_t)) // Timer Interrupt Control and Status Register
#define INTCTLSTAT_EVTINTSTAT34 (1 << 19)
#define INTCTLSTAT_EVTINTEN34 (1 << 18)
#define INTCTLSTAT_PRDINTSTAT34 (1 << 17)
#define INTCTLSTAT_PRDINTEN34 (1 << 16)
#define INTCTLSTAT_EVTINTSTAT12 (1 << 3)
#define INTCTLSTAT_EVTINTEN12 (1 << 2)
#define INTCTLSTAT_PRDINTSTAT12 (1 << 1)
#define INTCTLSTAT_PRDINTEN12 (1 << 0)

#define CMP0 (0x60/sizeof(uint32_t)) // Compare Register 0

#define CMP1 (0x64/sizeof(uint32_t)) // Compare Register 1

#define CMP2 (0x68/sizeof(uint32_t)) // Compare Register 2

#define CMP3 (0x6C/sizeof(uint32_t)) // Compare Register 3

#define CMP4 (0x70/sizeof(uint32_t)) // Compare Register 4

#define CMP5 (0x74/sizeof(uint32_t)) // Compare Register 5

#define CMP6 (0x78/sizeof(uint32_t)) // Compare Register 6

#define CMP7 (0x7C/sizeof(uint32_t)) // Compare Register 7

TIMER64P3[EMUMGT] = EMUMGT_FREE;
TIMER64P3[GPINTGPEN] = GPINTGPEN_GPENO12;
TIMER64P3[PRD12] = 3409;
TIMER64P3[TCR] = TCR_ENAMODE12_CONTINUOUS | TCR_CP12;
TIMER64P3[TGCR] = TGCR_TIMMODE_DUAL_UNCHAINED | TGCR_TIM12RS;