TMS320C6747: How do I decide the proper value of McASP X/RCLKCHK Registers?

Hi Yordan,

I do not think it relates to software. However, I am still expecting the response regarding this issue from the sw team.

Regards,
j-breeze

Hi,

Could you please let me know the current status regarding this thread?

Regards,
j-breeze

Hi Rahul,

Thank you for your reply, but I think it seems that you are misunderstanding.
I'm asking about McASP X/RCLKCHK Registers.

I'm not sure that how I decide the poper XMAX/XMIN field values.
Could you please let me know the formula to calculate the values?

Regards,
j-breeze

J-Breeze,

I am sorry, I misinterpreted the question. The Transmit Clock Failure Check and Recovery is usually used to detect a clock stop condition or when an external high clock is provided in the system and you want to ensure that there is no large variation in the in clock. 

the setting for XMIN and XMAX is totally dependent on the condition that you are trying to catch. For example, you need to first find out what the MCASP module clock value(using internal clock or AUXCLK) is as this is the system clock tick that is used to calculate XCNT.  this clock counts 32 high rate AHCLKX clocks. 

for setting this to catch any errors, I would recommend that in your setup when the clock is running normally, read the value of XCNT and based on that value you need to calculate the maximum tolerable deviation to setup XMIN and XMAX. This mechanism is described in fair amount of detail in the Clock Failure Detection of the MCASP chapter in the TRM.

for detecting clock stop condition, you can set the XMIN to 1 as when the AHCLKX clock stops, the count detect will be zero and will be less than 1 setup so will be enough to catch the clock failure condition. In order to catch incoming clock frequency variations, you may need some trial and error to set the correct XMIN and XMAX values based on XCNT value detected during normal condition.

Regards,

Rahul

Hi Raful,

I checked an old example called QuickStartOMAPL1x rCSL and found a code for the clock failure check below in it.
Can I refer to it?

  o quickStartOMAPL1x_rCSL_2.0
    (software-dl.ti.com/.../quickStartOMAPL1x_rCSL-2.0-Setup.zip)

  o mcasp.c
    (C:\ti\quickStartOMAPL1x_rCSL\OMAPL1x\rCSL_examples\evmOMAPL138\DSP_examples\mcasp)

    - Line 446~477

      //Transmit Clock Check Control Register

      //Set McASP Clock Zone Post Scaler

      //Note McASP is driven by SYSCLK2 which is SYSCLK/ which is a divide
      // by two of the main system clock 300/2 = (150MHz)
      CSL_FINST(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4);

      //Set XMAX Value
          //Notes: Prescale by 4
          //150/4 = 37.5 MHz

          //37.5MHz /24.576MHz (AUXCLK)  = 1.52587890625
          //32 Clock Counts * 1.52587890625 = 48.8 McASP System Clock Counts per every 32 AHCLKX
          //Counts

          //___________________________________________
          //32 ACLKs / 24.576MHz = 1.302uSec
        
          //48 Clocks / 37.5 MHz = 1.28 uSec
          //49 Clocks / 37.5 MHz = 1.306uSec
    
          //___________________________________________
          //Check
          //1.28 uSec < 1.302uSec < 1.306uSec
    
          //Include clock count buffer of 1 CLOCK
          //So Configure XMIN to be Uint8 47 (0x2F)
          //   Configure XMAX to be Uint8 50 (0x32)
 
      CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2F);    
      CSL_FINS(mcaspRegs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x32);
 
Regards,
j-breeze

Hi Rahul,

Thank you for your advice. I have one more question.
Could you please let me know what the clock count buffer is? Do I have to include it to calculate the XMAX/XMIN field values?

Sorry to bother you, but I'd like to ask you about it because it's a McASP Hardware spec,  not related to the code.

Regards,
j-breeze