TMS320C6742: HPI cannot write to L1D

Richard Breyer

Part Number: TMS320C6742
Other Parts Discussed in Thread: SYSBIOS

I have a custom peripheral attached to the HPI and I am trying to r/w to L1D. L2D works using the same configurations and peripheral signaling.

I have been reading up on cache and memory protection and I have not noticed that anything is amiss.

I have turned off caching completely, and ID local and ID x are completely unprotected. Still, the peripheral device is firing away,

under the impression that it is reading and writing but no memory changes.

I noticed that cpu writes are not allowed to L1P, but the info was pretty obscure.

In that vein, is there some important fact that I am missing about configuring the HPI to L1D conduit.

over 5 years ago

0 Yordan Kovachev over 5 years ago

TI__Guru**** 161600 points

Hi,

Which Processor SDK RTOS are you using?

Best Regards,
Yordan

0 Richard Breyer1 over 5 years ago in reply to Yordan Kovachev

Prodigy 70 points

We are not using BIOS. This is a single thread process.Most components are derived from starterware examples.

0 Richard Breyer over 5 years ago

Intellectual 430 points

This is code for hpi origination.

void hpiPinMuxSetup(void)
{

unsigned int svPinMuxHpi;
/* Actual pin multiplexing for HPI pinmux. Includes HINT */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(13)) = ALL_PINS_IN_REG_FOR_HPI;

/* pin multiplexing for HPI pinmux. */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(14)) = ALL_PINS_IN_REG_FOR_HPI;

/* pin multiplexing for HPI pinmux. */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(15)) = ALL_PINS_IN_REG_FOR_HPI;

/*
** Clearing the pins in context and retaining the other pin values
** of PINMUX16 register.
*/
svPinMuxHpi = (HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(16)) & \
~(SYSCFG_PINMUX16_PINMUX16_3_0 | \
SYSCFG_PINMUX16_PINMUX16_7_4));

/* Actual pin multiplexing for HD(0,1). */
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(16)) = \
(PINMUX16_HD0_ENABLE | \
PINMUX16_HD1_ENABLE | \
svPinMuxHpi);
}
* FUNCTION: hpiSetup
*
* PURPOSE : Configure HPI
*
* 1. Perform the necessary device pin multiplexing setup .
* ---Done in hpiPinMuxSetup
* 2. Configure the HPIENA and HPIBYTEAD bits in chip configuration 1 register
* (CFGCHIP1) in the System Configuration (SYSCFG) Module chapter.
* 3. Choose how HPIAR and HPIAW will be controlled by configuring the DUALHPIA
* bit in HPIC. -- responsibility of the host
* 4. Choose how halfword ordering will be handled by configuring the HWOB bit
* in HPIC. -- responsibility of the host
* 5. Choose how the HPI will respond to emulation suspend events by configuring
* the FREE and SOFT bits in PWREMU_MGMT.
* 6. Choose the desired initial addresses and write the addresses to HPIAW
* and HPIAR, appropriately. -- responsibility of the host
* 7. Set the correct host interrupt pin to input. --- by default at reset
* 8. Set up interrupt vector for HINT.
* 9. Release the HPI logic from reset by clearing the HPIRST -- responsibility
* of the host
*
******************************************************************************/

void hpiSetup(void)
{

/*
* Configure the HPIENA and HPIBYTEAD bits in chip configuration 1 register.
* enable the HPI for word addressing
*/

HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP1) |= \
(SYSCFG_CFGCHIP1_HPIENA << SYSCFG_CFGCHIP1_HPIENA_SHIFT);
//| \ This is the default
// (CSL_SYSCFG_CFGCHIP1_HPIBYTEAD_WORDADDR << CSL_SYSCFG_CFGCHIP1_HPIBYTEAD_SHIFT);
/*
* Choose how the HPI will respond to emulation suspend events by configuring
* the FREE and SOFT bits in PWREMU_MGMT.
*/
HWREG(SOC_HPI_0_REGS + HPI_PWREMU_MGMT) |= \
( HPI_PWREMU_MGMT_FREE << HPI_PWREMU_MGMT_FREE_SHIFT);

/*
* Set the correct host interrupt pin to input.
* Set correctly at reset
*
* Set the correct host interrupt vector.
* Set in sysbios. Int 4 Event 34 Prio highest Mask all
*/
IntRegister(C674X_MASK_INT14, hpiHostPostIsr);
IntEventMap(C674X_MASK_INT14, SYS_INT_UHPI_DSPINT);
IntEnable(C674X_MASK_INT14);
}