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TMS320C6748: NAND ECC calculation and flash programming

Charles Ung92
Intellectual 490 points
Part Number: TMS320C6748

We are building system with the C6746 together with the S34ML04G104Bxx01 nand flash. We are trying to preprogram the nand flash with a chip programmer but we are not sure what to do with the ECC in the spare area. The chip programmer that we are thinking of using only gives us a few options regarding the spare area usage and I am not sure is any of them matches the way TI is expecting them. Can you provide us some info  on this? Is there a way that is known to TI that can be used to preprogram the nand flash so it will work with the C6746/C6748?

Below is the list of options that our chip programmer provides:

ECC - Hamming (by Samsung): Double error found single error correction Hamming algorithm is employed to ensure data area reliability. Algorithm parameters are specified by Samsung - look at http://www.samsung.com/global/business/semiconductor/products/flash/downloads/applicationnote/ecc_algorithm_for_web_512b.pdf.

ECC - Hamming (2 x 256 Byte Frame) variant 1: Hamming ECC algorithm uses the same computational kernel as is specified for SmartMedia cards. It splits page into frames with 256 bytes in size, produces 3 bytes of control data and is capable to cover 1 single bit error per frame. Spare area layout is compatible with that one commonly used in Linux MTD driver. Also, control data bytes ordering respects Linux ordering.

ECC - Hamming (2 x 256 Byte Frame) variant 2: This ECC algorithm is identical to previous one (variant 1), but uses SmartMedia card original control data bytes ordering. It means, bytes ECC[0] and ECC[1] are switched in their respective positions.

My understanding is that none of this is what TI is using.

Regards,

Charles

  • 0
    TI__Guru**** 161600 points
    Hi Charles,

    I've notified the sw team. They will post their feedback directly here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 490 points
    Based on the conversation that I have with the chip programmer vendor, they can implement any custom ECC algorithm. They just need the info so they can implement it. Can you guys provide me the necessary info so I can pass that to the chip programmer vendor?

    Thanks,
    Charles
  • 0
    TI__Guru** 114410 points
    Charles,

    Do you plan to use the NAND for boot or only as non-volatile storage memory during runtime ? As you already know, the EMIF IP on the C6746 when ECC is enabled generates ECC data during write operation and can be used for performing upto 4bit Error correction over a block of 528 byte data.

    The ROM bootloader on the device expects the ECC data to be in the following format:
    processors.wiki.ti.com/.../DM365_Nand_ECC_layout

    The ECC mechanism used on the device is 4 bit Reed Solomon ECC as has been described here:
    processors.wiki.ti.com/.../NAND_ECC_Generation_for_DaVinci_Family_of_Devices

    The wiki also describes offline generation of ECC data using a host tool. You just need to ensure that the layout formatting matches with what the ROM bootloader uses so you can boot successfully.

    Let us know if you have any follow up questions.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 490 points
    Thanks for the info. I will pass that to the chip programmer vendor. And yes we are using the nand flash for booting.

    Thanks,
    Charles
  • 0 in reply to Charles Ung92
    Intellectual 490 points
    By the way, do you know a way to generate the AIS and RPRC images with the spare area data included in the file?
  • 0 in reply to Charles Ung92
    TI__Guru** 114410 points

    Charles.

    The spare area data is not included in the AIS and RPRC images. You generate the AIS images and RPRC images using the boot tools and store them in the normal page area of the NAND block. The spare area data is based on every 512 bytes of that user data stored on the page.Most of the tools that we use generate the AIS and RPRC images and use a tool that uses EMIF to generate the ECC data bits to store in the spare area. 

    I understand that you are trying to preflash the images in the NAND. Have you considered writing the images to one of our evaluation platforms with a 16 bit NAND  and then read back the page and the spare data information to a file and use that file for pre-programming your flash. As long as your NAND geometry is similar this should work:  the NAND on our evaluation platform has 2K pages with 64 byte spare area. 

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Intellectual 490 points

    Hi Rahul,

    Thanks for your suggestion. That was the alternative that I was thinking of but I was wondering is there a more direct way of doing this. But I guess not. Anyway thanks for all your help.

    Regards,

    Charles