C6000 Single Core DSP

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C6000 Single Core DSP

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SDRAM
Related Posts

  • Forum Post: Re: Changing Registers

    jyoung
    Tim, Thanks for the reply. We may have found our problem. When we read a double out of SDRAM the value is corrupted. When looking at memory the lower 32 bits are correct but the upper 32 are duplicates of bits 15-8. We are investigating this. Jim
    on Jul 16, 2008

  • Forum Post: Problems with C6713B and SDRAM

    Jeremy13304
    I am developing a DSPC6713B board with one chip of CPLD. The Timer and general purpose IO programs work normally. The input clock to the DSP CLKIN pin is 25MHz and dsp works on the frequency of 200MHz. When reset the DSP, the frequency of ECLKOUT,CLKOUT3, CLKOUT2 signal is correct as the datasheet...
    on Oct 21, 2009

  • Forum Post: Re: Problems with TMDSDSK6713 and daughter card TMDSFDCAFS86

    Richard Mersenski
    Hi, I am getting the same error message that you originally posted on the forum about. I am using CCS 3.1 and Bios 4.90.02.10 (according to the About window) and of course using a different source code program with the DSP/Bios configuration files. Can you remember what and where the problem was in...
    on Nov 13, 2009

  • Forum Post: Problems with SDRAM read and write in C6713B-200M DSP board

    Jerome Lau
    There are some strange problems with SDRAM read and write. A 1M*32bits*4banks SDRAM is used in my C6713B-200M board, that is for a 32-bit data read and write manipulation, the maximum address range is 0x400000(4M). I have developed two same boards with C6713B-200M. SDRAM works correctly in one board...
    on Nov 14, 2009

  • Forum Post: using the SDRAM problem on C6713 dsk board.

    Richard Mersenski
    I am trying to execute a program that is has its code and data stored on the external SDRAM of the C6713 DSK board. However, during a step through of my program in debugging, the program will execute correctly until a certain point and then while try to execute a certain function. The DSK "busy"...
    on Dec 9, 2009

  • Forum Post: locating buffer in SDRAM rather than internal

    Harry Thompson
    Hi, I have a C6713DSK talking with a THS1206 using the example program provided for the DCP (data converter plugin). My new problem is that when I move the buffer the data is read into from internal memory to the external SDRAM, which is located at 0x8000 0000 to 0x80FF FFFF, the program runs to...
    on Mar 19, 2010

  • Forum Post: Re: Select Device

    June He
    Dear Daniel Thanks for you suggestion, I have looked up in TI's website, and also have looked at the datsheet about TMS320C6745/6747 , However , no QFP [PYP suffix] were be founded, just only BGA [ ZKB suffix] package for TMS320C6747, and 6748 too. Are you sure that the 6747 include QFP(Quad...
    on Jul 3, 2010

  • Forum Post: Re: Select Device

    June He
    Yes, 256M of SDRAM space is enough, but more than two 16-bit EMIF interface are asked for FPGA and FLASH Another question is confused me : as you say , the 6745/6743 include 16-bit interface ,Are the 32-bit instruction can run in a 16-bit width SDRAM ? the 32-bit variable can be accessed or storaged...
    on Jul 3, 2010

  • Forum Post: Select Device

    June He
    Hi I am preparing for a new project , and some requests will be needed in follow for this design 1. 32-bit floating DSPs 2. Must be the QFP package , any other package such as BGA will not be accept 3. An 32-bit SDRAM interface needed, because a large size APP in this design, and the APP...
    on Jul 2, 2010

  • Forum Post: Re: Problems with SDRAM accessed by C6713B

    Keven74263
    The SDRAM has been configured using function "init_emif()" which isn't listed here. As you assumed, when I write a data through the memory window, it can't change successfully either. I tested the data pins and address pins with the digital oscilloscope, the wave displayed on the screen...
    on May 18, 2011

  • Forum Post: Re: [C6748] DDR2/mDDR Memory Controller Clock Stop Procedure

    Wesley Denlinger
    Hi Thomas and Tommy, Was a solution ever discovered for this problem? I am trying to put DDR in self refresh mode and am having trouble with steps 5 and 6 that are listed above. Conversely, I'll also need to know how to turn the clocks back on, but I assume that will be fairly obvious once I know...
    on Jul 8, 2011

  • Forum Post: DDR2 on custom board with C6748

    Admar Schoonen
    Hi We are developing a new product based on the C6748 (d800k006, so silicon revision 2). So far, we used the Logic EVM to develop the software, but now it is time to port this to our custom board. The custom board has a C6748 with an ISSI IS43DR16160A DDR2 chip. I'm trying to get this device...
    on Jun 29, 2011

  • Forum Post: Re: DSP selection for face recognition

    Nikhila Anand
    Dan, Thanks for the reply. I got much more ground on which the decision should be based. Well, the camera i've selected gives out standard JPEG data i.e. 24 bits per pixel that is integer, I guess. One VGA image with JPEG compression on an average takes about 600kB and about 12MB storage for...
    on Sep 23, 2011

  • Forum Post: Problem with DDR I/O calibration

    Alexander Sorg
    Hi, I am getting some problems trying to get my DDR2 (ISSI IS43DR16320B-25D) working with a c6748 DSP. Specifically I got problems during the VTP calibration routine: ......... CLRBIT(VTPIO_CTL, 0x00002000); // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction...
    on Oct 21, 2011

  • Forum Post: WHICH IS BEST FOR CODING ?

    Thiyagarajan . S
    HI, am planning to revise my c6745 kit with adc & dac for easy code writing.. suggest me , which type adc and dac will solve my easy code writing problem. am expecting to write program in soo short. so tell whicih is best ?????? which is best ? 1. Memory mapped based ADC &DAC. ...
    on Nov 15, 2011

  • Forum Post: BE Pins on C6713 QFP Package

    Ben Rosser
    Hi Everyone, I'm in the process of designing a circuit that uses a C6713 208 pin QFP package with the EMIF connected to four Micron SDRAM (4 bank) devices using CE0 - CE3. The issue that I've come across is that in the documentation it is stated that BE0 ad BE1 connect to the two bank enable...
    on Jan 25, 2012

  • Forum Post: DSP-SDRAM issue

    deepak siddharth
    Im using a custom board based whose EMIF configuration is based on DSK6211. It has Two 64Mbit SDRAM (MT48LC4M16A2TG) operating at 100Mhz. The issue now is when i load my program via code composer studio into SDRAM loaction i get is "Data verification failed at address 0x80000000. Please check...
    on Apr 5, 2012

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