C6000 Single Core DSP

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C6000 Single Core DSP

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  • Forum Post: Re: L2 ram latency

    Brad Griffis
    The internal memory is all single-cycle data access. This is mentioned on the first page of the data sheet under the "Enhanced Memory System" bullet. For instruction accesses everything must go through the L1P. So for a "hit" in L1P the instructions will execute in a single cycle...
    on Jun 13, 2008

  • Forum Post: A basic question about Cache Enable/Disabled Memory Access !

    Bilal_BumbleBee
    Hi, My name is peterson, I have a basic question about how processor access the memory elements in cache-enabled versus cache disabled scenarios. In spru656a, Chapter-1, Page 1-4, the C6000 DSP Cache user guide, the cache-hit/miss scenario is described. It tells that when cache is enabled, the...
    on Dec 25, 2010

  • Forum Post: Re: Possible memory corruption when using UPP IDMA on C6748

    Joe Coombs
    Dan, Are you explicitly making function calls to writeback/invalidate the cache when you're preparing your data buffers? This sounds like a cache coherence issue. I recommend the following procedures for transmit and receive operations: // prepare transmit buffer (generate sine wave, etc.)...
    on Sep 15, 2011

  • Forum Post: Re: Possible memory corruption when using UPP IDMA on C6748

    Joe Coombs
    Dan, Yes, this is an expected outcome when operating the uPP peripheral with cache enabled. The uPP DMA doesn't use caching, which presents an opportunity for memory incoherence between uPP and the DSP. It also explains why you saw the problem (somewhat) alleviated by using larger data buffers...
    on Sep 15, 2011

  • Forum Post: RE: Optimize processing speed for C6748 for math operations.

    Tuyen Nguyen
    Thanks a lot, Because the urgency of the project, I wanted to have quick techniques to optimize the speed without touching the code. But apparently, I cannot. So I spend time on digging into the code to apply compiler optimization for functions and loops and it improves a little bit. ABI change:...
    on May 1, 2012

  • Forum Post: RE: C674x Cache related questions

    Rahul Prabhu
    Documentation for those Cache APIs can be found here: http://rtsc.eclipse.org/cdoc-tip/xdc/runtime/knl/Cache.html The address you pass to the API, does not have to be cache line aligned, because the range of the addresses that the buffer covers is quantized to whole cache line. Similarly the byte...
    on May 11, 2012

  • Forum Post: Copy code from DDR into L1P SARAM

    Pruf
    Hello, We are using the C6748 device and CCS V5 with Code Generation Tools V7.3.8. Target: C6748 LCDK I would like to cut L1P memory in two halfs: lower range for SARAM (for fast algos) higher range for L1P cache. I do the following: 1. System reset 2. Disconnect target 3. Connect target (--> GEL...
    on Oct 25, 2012

  • Forum Post: RE: c6748 VPIF RAW capture from 12 bit CMOS sensor

    Andres Vahter
    Hello, Here is working VPIF driver for 8 bit capture: https://gist.github.com/andresv/4739017 and here is python script that can be used to convert bayer pattern data to RGB from image data memory dump (capChInfo.frame->frame.rpFrm.buf) http://pastebin.com/MW2xB6n3 I memcpyd from capChInfo.frame...
    on Mar 1, 2013

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