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EDMA3
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  • Forum Post: Re: Performance of EDMA3 Transfer Controller?

    TimHarron
    Please provide specifics of both transfers - what changed between the first and second transfer? Will you please also reference the specific section in the documentation?
    on Jun 18, 2008

  • Forum Post: Re: Performance of EDMA3 Transfer Controller?

    Brad Griffis
    What do you mean by "increase in DMA waits"? Are you saying it takes longer for the DMA to complete the transfer? Yes, if you're only doing 8-bit transfers then you should expect the DMA to transfer things inefficiently. That said, the whole point of the DMA is to not make the CPU wait...
    on Jun 22, 2008

  • Forum Post: Re: Performance of EDMA3 Transfer Controller?

    Venugopala
    Hi Satish, EDMA transfer efficiency depends on the type of transfer than the number of bytes of transfer. Say for the same amount of data transfer, 1D transfer time < 2D transfer time < 3D transfer time. This is becuase of the address generation logic and the strides of the EDMA H/w logic...
    on Dec 18, 2008

  • Forum Post: Re: TMS320c6424 EVM - emif

    TimHarron
    This is a tough question to answer because it depends on what you want to do. There isn't a typical (functional) CSL for the C6424 like there was for some of the older processors. The C6424 offering includes PSP drivers and a register-layer CSL you can find here . The EMIF is basically a "passive"...
    on May 20, 2009

  • Forum Post: Re: PSP McBSP Driver for C6424

    Umberto Amadei
    Gagan, I didn't use the PSP McBSP driver. I tried to remove from the PSP Audio driver and example (associated with McBSP driver) the part related to AIC33 configuration through I2C, but I had a lot of problems when I reduced the number of word in the frame (EDMA interrupt: BUFLEN parameter in audio_sample...
    on May 21, 2009

  • Forum Post: NDK 2.0 and EDMA bw management

    itsystems
    Hi, I've got a very strange problem when i tried to integrate one of our signal processing apps with TI NDK: forewords.... Our app is processing a 42Msamples/sec datastream coming from EMIFa with emifa bw of about 25%. The deadline for transfers is very short. We are using DSK6455 1GHz...
    on Aug 25, 2009

  • Forum Post: C6457 EMIF-HPI Link

    Craig Neely
    Hello, I'm designing a board around the C6457 processor and I can't find an important bit of info in any of the data sheets. Which bus voltage do the EMIFA, HPI, and GPIO peripheral ports use? 1.8V or 3.3V? I'm embarrassed to ask something so basic, but I've looked everywhere I...
    on Oct 11, 2009

  • Forum Post: How do you turn off the UART Transmitter at the end of an EDMA transfer?

    Michael Manness
    I'm having trouble turning off the UART transmitter in an automatic DMA transfer to the THR register in the UART. The sequence of operations is: 1) Incoming characters hit the UART RBR Register triggering an EDMA transfer in the UART RX channel into "Buffer 1". 2) The TCCHEN bit in...
    on Oct 30, 2009

  • Forum Post: Improve Read from FPGA via EMIFA using EDMA

    Francisco Aguilar
    Hello, could you please help in the following issue? We're configuring EDMA in the TMS320C6455 in order to send/receive data to/from FPGA via EMIFA bus. We've found a problem in the EDMA configuration when we are trying to read from FPGA. We detect in the time diagram that every 20 cycles, the...
    on Nov 5, 2009

  • Forum Post: UART read using EDMA3 OMAPL137

    Arye Lerner
    Hi, I am trying to read data of 8 bytes from UART2 using EDMA3. I used the LLD driver for EDMA (C:\Program Files\Texas Instruments\edma3_lld_01_10_00_01\packages\ti\sdo\edma3\drv\sample\src). The idea is to generate an interrupt at the end of the receive. That is what I got working so far: 1) I...
    on Nov 10, 2009

  • Forum Post: Re: EDMA3

    Arye Lerner
    Hi, Thank you, I'll do that, it is a good idea! I am using interrupt at the start, and then trying to activate EDMA in linking to the same PaRAM set. I managed to activate second transfer, and I get the data from second transfer, just for some reason an event interrupt is not generated the...
    on Nov 17, 2009

  • Forum Post: EDMA syncronization

    Arye Lerner
    Hello, I am using EDMA3 to write to UART2. I am activating it in manual triggered mode, and configuring it so each time the transfer is complete, an interrupt is generated, where the new transfer parameters are set. This works fine, as long as I set a break point in interrupt routine, but when...
    on Nov 22, 2009

  • Forum Post: Is OMAP35x EDMA3 compatible with DM6437 EDMA3?

    LinceE2C
    Hello, I use the DM6437 EDMA3 and now I need to migrated it to OMAP3530. I looks the sheets and I discover than they are very similars but at http://software-dl.ti.com/dsps/dsps_registered_sw/sdo_sb/targetcontent/psp/edma3_lld/index.html I saw that there are one different version for each one. This...
    on Dec 9, 2009

  • Forum Post: McASP multiple serializers & EDMA3

    Szymon Kuklinski
    Hi I have a question about DMA transfers when using McASP with multiple serializers on OMAP-L138. In my situation it looks like that: - I have 8 serializers programmed as input and 8 programmed as output - I'm transmitting/receiving 32 8-bit slots on every serializer - so far the transmitters...
    on Feb 22, 2010

  • Forum Post: Re: McASP multiple serializers & EDMA3

    Szymon Kuklinski
    After some time spent understanding McASP and EDMA I think I know enough to proceed further. What I'm planning to do is to place McASP and EDMA configuration code inside a DSP program which is to be loaded using DSPLink. My concern is that writing LLD EDMA code and executing it on the DSP while Linux...
    on Mar 9, 2010

  • Forum Post: Re: McASP multiple serializers & EDMA3

    Szymon Kuklinski
    I looked into the registers and noticed that when I call EDMA3_DRV_linkChannel (hEdma, chIdTX0, chIdTXLink0); the PaRAM of chIdTX0 doesn't get reloaded but instead a NULL PaRAM set gets written. When I explicitly write the LinkReload address to the correct register McASP starts up just fine. There...
    on Mar 10, 2010

  • Forum Post: Re: [OMAP-L137] IPR does not set in EDMA3 LLD when setting a second TCC

    Anuj Aggarwal
    Are you setting the trigger word properly? You can use EDMA3_DRV_setQdmaTrigWord() for this. Please note that the trigger word should be written in the end after you set all other fields of the corresponding PaRAM Set. Please refer to edma3_lld_01_11_00_03\examples\edma3_driver\src\qdma_test.c for...
    on Mar 30, 2010

  • Forum Post: Question on EDMA ACNT

    Fan36545
    Hi there, I have a quick question on EDMA. On the page 74 of spru966b.pdf, the example said there are 256 words (I supposed 2 bytes word) to be copied. But on the next page, ACNT=0x100h, BCNT = 0x1h and CCNT = 0x1h, which means there are ACNT*BCNT*CCNT = 256 bytes will be copied. I am so confused...
    on Apr 1, 2010

  • Forum Post: No EDMA3 transfers to MCASP

    Jim Patterson42697
    I'm sure that I will recognize this as a "Doh!" question when I find the answer... I am unable to get the EDMA3 to respond to MCASP transmit events in my 6424 application. I have MCASP0 configured for 4 output serializers, transmitting 16-bit data padded to 32-bits in I2S output format...
    on Apr 7, 2010

  • Forum Post: Urgent!!! ACPY3_wait() function doesn't wait really

    hasan turken
    I am using EVMOMAPL137 and trying to use EDMA3 with ACPY3 API I am able to copy data from one location to another(from external memory(SDRAM) to internal(L2)). But when I want to use ACPY3_wait() function in order to wait the transfer be completed, I fail. I am trying to read just after the...
    on Apr 13, 2010

  • Forum Post: Re: edma3 AXEVT signal not being generated from MCASP module

    caleb crome
    I fixed the problem, but I'm not 100% sure of the exact fix. One problem is that I used the McBSP example code for the DMA. That was a problem because it only takes 1 word per DMA event, so A count was wrong. I send 32, 32-bit words at a time, so A count must be the same as the FIFO RNUMEVT and WNUMEVT...
    on Jul 22, 2010

  • Forum Post: Re: EMIF with EDMA example

    Vladimir Podosinov
    I had 2 questions to you. First, if I do not want DSP to take care of the transfer, but rather make it automatically restart after the transfer is done. For example if I have ping-pong buffering, can I set up either QDMA or DMA to self restart as soon as one of the buffers is transferred? (I think I...
    on Jul 24, 2010

  • Forum Post: Issue faced while using QDMA

    Abhi44810
    Use Case of QDMA: QDMA is used to single data transfer of 6K from external memory to internal memory. Configuration/setting carried out to get QDMA in effect: 1. EDMA driver initialisation 2. By using handle of EDMA driver, QDMA channel is created/initialised. Provided the callback function...
    on Aug 4, 2010

  • Forum Post: DDR2 problem on 320C6424

    Vitaliy
    The test program is loaded correctly and works from DDR2 memory. But is it worth to include DMA (EDMA3) exchange with DDR2 immediately dies. He dies when transferring buffer from L2 to DDR2. What to do - I'll never know. Quartz 25MHz. PLL is programmed to 162.5 Mhz Initialization is as follows: ...
    on Sep 9, 2010

  • Forum Post: issue About csl_6455 example " edma_interrupt "?

    du ke
    (Please visit the site to view this file) There is a problem of using the csl_6455 example"edma_interrupt". when no modify ,the EDMA can work properly, data transfer completely. but when I mask this section" if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff, dstBuff,TRUE) == FALSE...
    on Oct 25, 2010
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