• Join
  • Sign In with my.TI Login
Texas Instruments
  • Products
  • Applications
  • Tools & Software
  • Support & Community
  • Sample & Buy
  • About TI
Sample & Purchase Cart Sample & Purchase Cart
  • Search
  • Advanced
TI E2E™ Community
  • Support Forums
  • Blogs
  • Groups
  • Videos
  • 简体中文
  • More ...
TI Home » TI E2E Community » Support Forums » Embedded Software » BIOS » BIOS forum » "Cache settings were changed in user configuration."
Share
BIOS
  • Forum
  • Announcements
Options
  • Subscribe via RSS

Forums

"Cache settings were changed in user configuration."

This question is answered
Kurt Jensen
Posted by Kurt Jensen
on Jan 27 2012 10:13 AM
Genius4880 points

I tried to decipher this message but I am still confused as to exactly what is being recommended that I do.

"Cache settings were changed in user configuration. User configuration options will override platform settings. Check your memory map to make sure that Cache does not conflict with your L1/L2 memory placement. To avoid conflicts between L1/L2 memory and cache, we recommended specifying cache sizes along with memory sizes in a platform package."

How do I check "your memory map to make sure that Cache does not conflict with your L1/L2 memory placement. "

How do I specify "cache sizes along with memory sizes in a platform package." ?

Report Abuse
  • Reply
You have posted to a forum that requires a moderator to approve posts before they are publicly available.
All Replies
  • Sasha Slijepcevic
    Posted by Sasha Slijepcevic
    on Jan 27 2012 13:22 PM
    Genius15700 points

    Kurt,
    here is a long description of memory management in RTSC, that also describes cache settings. The short version of it is that a platform defines how much of L1/L2 memory is cache, and how much is available for section allocations. The easiest way to check what are the default values for your platform is to use Platform Wizard and to try creating a new platform based on the platform you are currently using. Select Device Family/Device Name that corresponds to the device you are using, click Next, and then click on Import and select the platform you are using. Look at L1P, L1D and L2 parameters and you'll see how much is allocated to cache.
    You can alternatively look at the RTSC Package documentation, where you need to find your platform and check the values for l1DMode, l1PMode and l2Mode.

    The message you are quoting is saying that the cache setting in the platform are different from the ones in your script. Therefore, you have to configure the platform to avoid having program sections conflict with cache.  

    Now, you can continue with building a new platform with Platform Wizard. Change L1P, L1D and L2 cache settings to fit your choices in the config script and create your new platform. There is a Platform Wizard demo that describes all the steps you need to take.

    If my reply answers your question please mark the thread as answered.

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • Kurt Jensen
    Posted by Kurt Jensen
    on Jan 27 2012 14:04 PM
    Genius4880 points

    Wow!  Seems like a lot of work just to get a bit of L2 cache. 

    I will need some time to study this.  Thanks.

     

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • Kurt Jensen
    Posted by Kurt Jensen
    on Jan 30 2012 09:51 AM
    Genius4880 points

    This morning I tried to create a new platform.  I changed the L2 to 256k cache. Then I saved the new platform to a custom location.

    In Properties, General, RTSC I found and selected my new platform.  After rebuilding I checked the device specific cache page, C6x/Cache.  It says that "L2 is  all SRAM".  If I "Add the Cache module to my configuration" then select "L2 cache size" = 256k, then the build gives me the same error "Cache settings were changed in user configuration."

    How do I do this in ccs5?

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • judahvang
    Posted by judahvang
    on Feb 01 2012 17:28 PM
    Genius16765 points

    Kurt,

    1)  What version of BIOS are you using?

    2)  You need to make sure your cache configuration and L1/L2 memory segments do not overlap.  Best way to do this is to look at the datasheet for your specific device.
          What device or platform are you trying to build for?

    If you've made a new platform with the right cache settings, you shouldn't have to change the cache settings in your app.cfg file.

    Judah

    If my reply answers your question please mark the thread as answered

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • Kurt Jensen
    Posted by Kurt Jensen
    on Feb 01 2012 17:51 PM
    Genius4880 points
    spiricon_platforms_evm6748.zip

    1) SYS/BIOS 6.33.01.25

    2) I understand the choices for my device.  Now I want to implement those choices in bios settings.

    3) c6748

    yesterday, after supposedly creating a new custom platform with L2 cache set to 256k, and still getting a warning, I went back to ti.platforms.evm6748.  I then reloaded the CFG and looked at the cache settings - the "L2 cache size" is now "Amount of cache is 256k".  now, today, is displays "L2 is all SRAM".  I tried to duplicate yesterday's "256k" but failed.

    4) As far as I can tell I need to create a new custom platform with L2 cache set to 256k.  I thought I did.  how do I do this?

    5) I have attached the platform I created.  can you look at it?

    6) how do I edit my new custom platform?

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • judahvang
    Posted by judahvang
    on Feb 01 2012 18:21 PM
    Verified Answer
    Verified by Kurt Jensen
    Genius16765 points

    Kurt,

    I took your custom platform and successfully build the SYSBIOS - Clock example with it.  Your platform looks fine.  I can see that basically you set L2 to be 256K so the IRAM memory segements goes away since IRAM is supposed to be any part of L2 that is SRAM.  Then you placed everything out in DDR.

    1.  Yes, for what you are doing, creating a new platform makes sense.

    2.  You can edit your custom platform in CCS by doing:
          a.  Select  "File->New->Other"
          b.  Select  "Edit/View RTS Platform"
          c.  Point to your repository with your platform
          d.  You should see your platform under "Package Name".  Select your platform and hit "Next"

    3.  Make sure your project is pointing to your platform.  If your platform is not on the package path, you can add it to the package path.  I have included a screen shot of the
         project I made and how I point to your platform by adding the package path to my project.

    Judah

    If my reply answers your question please mark the thread as answered

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • Kurt Jensen
    Posted by Kurt Jensen
    on Feb 02 2012 08:47 AM
    Genius4880 points

    I now see the L2 cache set to 256k after setting "Other Repositories"...sort of...

    3a) After creating the custom project a path to my packages was added to the Order tab (sibling to the Products and Repositories tab)  In every case I was able to select my custom platform without adding "Other Repositories".

    3b) I have two projects that use the same CFG.  A production code project owns the CFG.  A unit test project links to the CFG. I added a path to Other Repositories in both projects and selected my custom platform in both projects.  In the production project it says "L2 is all SRAM". In the unit test project it says, "Amount of cache is 256k". 

    I unchecked "Add the Cache module to my configuration" in the production project, saved the CFG, and exited ccs5.  I restatred ccs5 then looked at the "Device-specific Cache support".  On both projects it now says "Amount of L2 cache is 256k". At this point I guess I can trust that it really is set the same as the platform default regardless of what is displayed.

     

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
  • judahvang
    Posted by judahvang
    on Feb 02 2012 10:43 AM
    Genius16765 points

    Kurt,

    If you are familiar with ROV plugin, run your program to main() and then open up the ROV plugin and view the Cache Module settings.
    This should confirm that your cache settings got set correctly.

    Judah

    If my reply answers your question please mark the thread as answered

    Report Abuse
    • Reply
    You have posted to a forum that requires a moderator to approve posts before they are publicly available.
TI E2E™ Community
  • Support Forums
  • Blogs
  • Videos
  • Groups
  • Site Support & Feedback
  • Settings
TI E2E™ Community Groups
  • TI University Program
  • Make the Switch
  • Microcontroller Projects
  • Motor Drive & Control
Other Communities
  • Deyisupport
  • Designsomething.org
  • beagleboard.org
  • TI on Element 14
  • TI on TechXchangeSM
Other Technical & Support Resources
  • WEBENCH® Design Center
  • Product Information Centers
  • Technical Documents
  • TI Design Network
  • TI Technical Articles
  • TI Training

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

Follow Us Texas Instruments on Facebook Texas Instruments on Twitter Texas Instruments on LinkedIn Texas Instruments on Google+
TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
embedded processors, along with software, tools and the industry’s largest sales/support staff.

© Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy Policy | Terms of Use