I'm using C674x core DSP, and initiailize EDMA driver with EDMA3 LLD library, all things look likes done, but can't transfer the data correctly. I requested two dma channels resource for McASP servicing, two link channels for every dma channel, Setting corresponding PaRAM, and linked them with ping pong mode for transfer data between memory and McASP FIFO.
At last, there wasn't any data tested when I tested the transfer parameters on custom board. Anyone have this problem?
To understand the issue, I need more info, like,
1. Are you using the BIOS PSP released by the TI?
2. Are you using the EDMA package released by TI?
3. Are you using the DSP/BIOS or the SYS/BIOS?
4. Is McASP using the internal clock or the external clock?
5. Are you able to to probe the McASP clock and is it as per the configuration?
6. Have you observed any error interupt being generated? either for McASP or from EDMA.
7. Did you check the IPR register in EDMA for any pending interrupt?
BTW, Can you please test the EDMA application first on your custom board and then move on to the McASP application?
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I'm sorry that I didn't state the problem clearly. I'm using C6A8168 device, and the BIOS/PSP driver released by TI still cann't support this platform. Certainly, I'm using EDMA LLD package released by TI in EzSDK 5_02_02_60 including SYS/BIOS 6_32_01_38 , I haven't re-built them before.
McASP using external clock, 8KHZ sync clock and 2MHZ sample clock. I have probed the McASP clock and it's work for per configuration, I also check the EDMA region 1(for DSP) registers' value and all McASP registers' value are normal(compared with ARM McASP driver).
I'll test the EDMA application on my custom board.
I test the EDMA application on my custom board, and the ping pong example can't excute ISR, so I return to test my own EDMA application.
And now I can receive data from McASP1 FIFO using special dma channel 11 , but can't transfer data from memory to McASP1 FIFO using special dma channel 10.
1. I am using FIFO for tx destination address and rx source address.
2. I malloc the block memory for receiving the data from FIFO and transfering the other block memory data to FIFO.
3. The source and destination address mode are both INCR mode.
4. Both tx and rx transfer mode are AB sync mode for EDMA ping pong transfer.
5. I checked the ER value, when using tx mode(channel 10), it's 0x800, and it's 0x400 using rx mode(channel 11), seem like opposit. Why?
I don't know Why EDMA can't transfer the data, and I pasted my EDMA application below. Can you check whether my parameters set incorrectly or not? Thank you!
Let me check the shared file.
Have you found out the problem in my EDMA application?
I have gone through the configurations done by you.
Can you please revisit the EDMA3_DRV_requestChannel()? The API description is available in the file edma3_lld_<Version>\packages\ti\sdo\edma3\drv\edma3_drv.h
In the EDMA3_DRV_requestChannel(), second and the third paramater should be the EDMA event ID of the McASP (receive or the transmit).
Please refer the device manual to get the EDMA event IDs.
In case, if you want to refer the EDMA configuration of the mcasp, please refer the PSP available in the link http://software-dl.ti.com/dsps/dsps_public_sw/psp/BIOSPSP/03_00_01_00/index_FDS.html. This PSP is not for C6A8168 device, it is just for reference to know how to use the EDMA API's in the driver.
I changed the EDMA event ID to mcasp sync event and even if I didn't use the event ID, I set dma channel to map tcc in EDMA3_DRV_GblConfigParams. Hence this parameter shoudn't be the reason.
I think that EDMA3 service McASP peripheral receive the data from it and move to the memory. If the memory is in DDR, use cache flush and invalidate the block memory then use them, or don't use it, is that right?
When I check the ER , EER value respectively tx and rx transfer, EER value is true, but ER value can't show any value. Why?
I also referenced the BIOS_PSP EDMA and MCASP drivers, my program's progress the same as it basically. I don't know how to fix it. Can you find any other informations for my EDMA application? Thank you !
Did you check the IPR register for any pending interrupts?
I have checked all register status, the value are true...I really don't know the reason why the application have this problem.
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